plltb.v

用VHDL写的数字锁相环程序 pll.vhd为源文件 pllTB.vhd为testbench

/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
///
/// File        : pllTb.v
/// Author      : Parthus Technologies PLC
/// Date	: Mon Feb 17 06:08:33 2003
/// Info	: Job No = 12364215
///_______________________________________________________________________
///
///        Copyright (c) 2002 Parthus Technologies PLC.
///
/// This code is confidential and proprietary product of Parthus. Any
/// unauthorized use, reproduction or transfer of this code is strictly
/// prohibited.
///_______________________________________________________________________
///
/// Description: This file contains a template testbench for the 
/// 	         pllDig.v & pllCore.v modules.
///		 
///_______________________________________________________________________
///
///
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////


`timescale 1ns/1ps	//the precision is specified as 1ps. This can be
			//decreased to a minimum of 100ps

// include verilog code for PLL core 
`include "./pll.v"

`define SIM_DURATION 230000


module tb_pllxpert();

reg porL, refClk, sleepL, forceBypass;
reg [7:0] FBD;
reg [7:0] IPD;

wire FBD0,FBD1,FBD2,FBD3,FBD4,FBD5,FBD6,FBD7;
wire IPD0,IPD1,IPD2,IPD3,IPD4,IPD5,IPD6,IPD7;

wire xClk01;
wire xClk02;
wire xClk03;


wire pllLock, sysResetL;

real half_refClk_period;

xtop4215 Ixtop4215
	 (.porL(porL), .sleepL(sleepL), .refClk(refClk), .forceBypass(forceBypass),
	  .FBD0(FBD0), .FBD1(FBD1), .FBD2(FBD2), .FBD3(FBD3),
	  .FBD4(FBD4), .FBD5(FBD5), .FBD6(FBD6), .FBD7(FBD7),
	  .IPD0(IPD0), .IPD1(IPD1), .IPD2(IPD2), .IPD3(IPD3),
	  .IPD4(IPD4), .IPD5(IPD5), .IPD6(IPD6), .IPD7(IPD7),
	  .xClk01(xClk01),
	  .xClk02(xClk02),
	  .xClk03(xClk03),
	  .pllLock(pllLock), .sysResetL(sysResetL));


assign IPD0 = IPD[0];
assign IPD1 = IPD[1];
assign IPD2 = IPD[2];
assign IPD3 = IPD[3];
assign IPD4 = IPD[4];
assign IPD5 = IPD[5];
assign IPD6 = IPD[6];
assign IPD7 = IPD[7];

assign FBD0 = FBD[0];
assign FBD1 = FBD[1];
assign FBD2 = FBD[2];
assign FBD3 = FBD[3];
assign FBD4 = FBD[4];
assign FBD5 = FBD[5];
assign FBD6 = FBD[6];
assign FBD7 = FBD[7];


initial // Main test routine, Initialise inputs and do tests
  begin
  refClk = 1'b0 ;
  sleepL = 1'b1;
  porL = 1'b0;
  forceBypass = 1'b0;

  IPD = 0;
  FBD = 63;

  half_refClk_period =  111.111111;

  doReset ; // Perform the reset as defined by task ;

  $display("Reset at time = %f",$realtime);

  #46000.000000 doSleep;
  $display("Taken out of sleep mode at time = %f",$realtime);

  #34500.000000 FBD = 36;
  half_refClk_period =  85.535882;

  $display("set FBD = 36, at time = %f",$realtime);

  #5750.000000 doReset;
  $display("Reset, at time = %f, in order to resume correct operation",$realtime);

  #34500.000000 FBD = 113;
  half_refClk_period =  158.503725;

  $display("set FBD = 113, at time = %f",$realtime);

  #5750.000000 doReset;
  $display("Reset, at time = %f, in order to resume correct operation",$realtime);

  #34500.000000 FBD = 255;
  #5750.000000 doReset;
  $display("set FBD = 255, at time = %f. This an invalid selection",$realtime);

  half_refClk_period =  111.111111;

  #5750.000000 FBD = 63;
  #5750.000000 doReset;
  $display("Reset, at time = %f, in order to resume correct operation",$realtime);

  #46000.000000 forceBypass = 1'b1;
  doReset;
  $display("going into byPass mode, at time = %f",$realtime);


  end

initial
  begin
  $dumpfile("./VCD_FILE.out");
  $dumpvars(1,tb_pllxpert);

  #`SIM_DURATION;

  $finish; // Simulation Finish time
  end 

always refClk = #half_refClk_period ~refClk;

task doReset ;                
  begin
  porL = 1'b0 ;
  #1000 porL = 1'b1;
  end
endtask

task doSleep ;                
  begin
  sleepL = 1'b0 ;
  #1000 sleepL = 1'b1;
  end
endtask


endmodule