dff.v

发一个基于ModelSim仿真的Verilog源代码包

  /******************************************************/
/*       module dff                                   */
/******************************************************/
/* A D flip-flop module. */
module dff(D,Q,Clock,Reset); // N.B. reset is active-high.

parameter CARDINALITY = 1;

output [CARDINALITY-1:0] Q; 
input  [CARDINALITY-1:0] D;
input Clock,Reset;

//parameter CARDINALITY = 1; 
reg [CARDINALITY-1:0] Q;
wire [CARDINALITY-1:0] D;

//!!!Asyn ->Reset, Below is the only synthetizable code; 


always @(posedge Reset or posedge Clock) 
    begin
      if (Reset)  Q <= 0;
	  else	 Q<=D; 
	end 
endmodule