fen_translate.v

verilog

// Xilinx Verilog netlist produced by netgen application (version G.23)
// Command      : -intstyle ise -w -ofmt verilog -sim fen.ngd fen_translate.v 
// Input file   : fen.ngd
// Output file  : fen_translate.v
// Design name  : fen
// # of Modules : 1
// Xilinx       : E:/Xilinx
// Device       : 2s50pq208-6

// This verilog netlist is a simulation model and uses simulation 
// primitives which may not represent the true implementation of the 
// device, however the netlist is functionally correct and should not 
// be modified. This file cannot be synthesized and should only be used 
// with supported simulation tools.

`timescale 1 ns/1 ps

module fen (
  reset, f, f4t, f5t
);
  input reset;
  input f;
  output f4t;
  output f5t;
  wire reset_IBUF;
  wire f_BUFGP;
  wire f4t_OBUF;
  wire f5t_OBUF;
  wire _n0000;
  wire _n0002;
  wire _n0003;
  wire _n0014;
  wire f4t_N55;
  wire N700;
  wire \_n00001/O ;
  wire \i_Madd__n0000__n00061/O ;
  wire \Mmux__n0003_Result1/O ;
  wire \_n0004<2>1/O ;
  wire \_n0004<1>1/O ;
  wire \_n0004<0>1/O ;
  wire \i_Madd__n0000_Mxor_Result<2>_Result1/O ;
  wire \i_Madd__n0000_Mxor_Result<1>_Result1/O ;
  wire \f_BUFGP/IBUFG ;
  wire GSR = glbl.GSR;
  wire \f4t_OBUF.GTS.TRI ;
  wire GTS = glbl.GTS;
  wire \f5t_OBUF.GTS.TRI ;
  wire VCC;
  wire GND;
  wire \NlwInverterSignal_f4t_OBUF.GTS.TRI/CTL ;
  wire \NlwInverterSignal_f5t_OBUF.GTS.TRI/CTL ;
  wire [2 : 0] j;
  wire [2 : 0] _n0004;
  wire [2 : 0] i;
  wire [2 : 0] i__n0000;
  defparam j_1.INIT = 1'b0;
  X_SFF j_1 (
    .I(_n0004[1]),
    .SRST(f4t_N55),
    .CLK(f_BUFGP),
    .O(j[1]),
    .CE(VCC),
    .SET(GND),
    .RST(GSR),
    .SSET(GND)
  );
  defparam j_0.INIT = 1'b0;
  X_SFF j_0 (
    .I(_n0004[0]),
    .SRST(f4t_N55),
    .CLK(f_BUFGP),
    .O(j[0]),
    .CE(VCC),
    .SET(GND),
    .RST(GSR),
    .SSET(GND)
  );
  defparam i_1.INIT = 1'b0;
  X_SFF i_1 (
    .I(i__n0000[1]),
    .SRST(_n0002),
    .CLK(f_BUFGP),
    .O(i[1]),
    .CE(VCC),
    .SET(GND),
    .RST(GSR),
    .SSET(GND)
  );
  defparam _n00141.INIT = 4'h5;
  X_LUT2 _n00141 (
    .ADR0(f4t_OBUF),
    .O(_n0014),
    .ADR1(GND)
  );
  defparam i_2.INIT = 1'b0;
  X_SFF i_2 (
    .I(i__n0000[2]),
    .SRST(_n0002),
    .CLK(f_BUFGP),
    .O(i[2]),
    .CE(VCC),
    .SET(GND),
    .RST(GSR),
    .SSET(GND)
  );
  defparam i_0.INIT = 1'b0;
  X_SFF i_0 (
    .I(i__n0000[0]),
    .SRST(N700),
    .CLK(f_BUFGP),
    .O(i[0]),
    .CE(VCC),
    .SET(GND),
    .RST(GSR),
    .SSET(GND)
  );
  defparam f4t_0.INIT = 1'b0;
  X_SFF f4t_0 (
    .I(_n0014),
    .SRST(f4t_N55),
    .CE(_n0000),
    .CLK(f_BUFGP),
    .O(f4t_OBUF),
    .SET(GND),
    .RST(GSR),
    .SSET(GND)
  );
  defparam f4t_N551.INIT = 4'h5;
  X_LUT2 f4t_N551 (
    .ADR0(reset_IBUF),
    .O(f4t_N55),
    .ADR1(GND)
  );
  defparam f5t_1.INIT = 1'b0;
  X_SFF f5t_1 (
    .I(_n0003),
    .SRST(f4t_N55),
    .CLK(f_BUFGP),
    .O(f5t_OBUF),
    .CE(VCC),
    .SET(GND),
    .RST(GSR),
    .SSET(GND)
  );
  defparam j_2.INIT = 1'b0;
  X_SFF j_2 (
    .I(_n0004[2]),
    .SRST(f4t_N55),
    .CLK(f_BUFGP),
    .O(j[2]),
    .CE(VCC),
    .SET(GND),
    .RST(GSR),
    .SSET(GND)
  );
  X_BUF reset_IBUF_2 (
    .I(reset),
    .O(reset_IBUF)
  );
  X_BUF f4t_OBUF_3 (
    .I(f4t_OBUF),
    .O(\f4t_OBUF.GTS.TRI )
  );
  X_BUF f5t_OBUF_4 (
    .I(f5t_OBUF),
    .O(\f5t_OBUF.GTS.TRI )
  );
  X_IPAD f_5 (
    .PAD(f)
  );
  X_IPAD reset_6 (
    .PAD(reset)
  );
  X_OPAD \f4t.PAD  (
    .PAD(f4t)
  );
  X_OPAD \f5t.PAD  (
    .PAD(f5t)
  );
  X_BUF \_n00001/LUT3_L_BUF  (
    .I(\_n00001/O ),
    .O(_n0000)
  );
  defparam _n00001.INIT = 8'h04;
  X_LUT3 _n00001 (
    .ADR0(i[2]),
    .ADR1(i[0]),
    .ADR2(i[1]),
    .O(\_n00001/O )
  );
  X_BUF \_n00021/LUT4_D_BUF  (
    .I(_n0002),
    .O(N700)
  );
  defparam _n00021.INIT = 16'h02FF;
  X_LUT4 _n00021 (
    .ADR0(i[0]),
    .ADR1(i[1]),
    .ADR2(i[2]),
    .ADR3(reset_IBUF),
    .O(_n0002)
  );
  X_BUF \i_Madd__n0000__n00061/LUT1_L_BUF  (
    .I(\i_Madd__n0000__n00061/O ),
    .O(i__n0000[0])
  );
  defparam i_Madd__n0000__n00061.INIT = 4'h5;
  X_LUT2 i_Madd__n0000__n00061 (
    .ADR0(i[0]),
    .ADR1(GND),
    .O(\i_Madd__n0000__n00061/O )
  );
  X_BUF \Mmux__n0003_Result1/LUT4_L_BUF  (
    .I(\Mmux__n0003_Result1/O ),
    .O(_n0003)
  );
  defparam Mmux__n0003_Result1.INIT = 16'hAA96;
  X_LUT4 Mmux__n0003_Result1 (
    .ADR0(f5t_OBUF),
    .ADR1(j[2]),
    .ADR2(j[0]),
    .ADR3(j[1]),
    .O(\Mmux__n0003_Result1/O )
  );
  X_BUF \_n0004<2>1/LUT3_L_BUF  (
    .I(\_n0004<2>1/O ),
    .O(_n0004[2])
  );
  defparam \_n0004<2>1 .INIT = 8'h68;
  X_LUT3 \_n0004<2>1  (
    .ADR0(j[1]),
    .ADR1(j[0]),
    .ADR2(j[2]),
    .O(\_n0004<2>1/O )
  );
  X_BUF \_n0004<1>1/LUT2_L_BUF  (
    .I(\_n0004<1>1/O ),
    .O(_n0004[1])
  );
  defparam \_n0004<1>1 .INIT = 4'h6;
  X_LUT2 \_n0004<1>1  (
    .ADR0(j[1]),
    .ADR1(j[0]),
    .O(\_n0004<1>1/O )
  );
  X_BUF \_n0004<0>1/LUT3_L_BUF  (
    .I(\_n0004<0>1/O ),
    .O(_n0004[0])
  );
  defparam \_n0004<0>1 .INIT = 8'h45;
  X_LUT3 \_n0004<0>1  (
    .ADR0(j[0]),
    .ADR1(j[1]),
    .ADR2(j[2]),
    .O(\_n0004<0>1/O )
  );
  X_BUF \i_Madd__n0000_Mxor_Result<2>_Result1/LUT3_L_BUF  (
    .I(\i_Madd__n0000_Mxor_Result<2>_Result1/O ),
    .O(i__n0000[2])
  );
  defparam \i_Madd__n0000_Mxor_Result<2>_Result1 .INIT = 8'h6A;
  X_LUT3 \i_Madd__n0000_Mxor_Result<2>_Result1  (
    .ADR0(i[2]),
    .ADR1(i[0]),
    .ADR2(i[1]),
    .O(\i_Madd__n0000_Mxor_Result<2>_Result1/O )
  );
  X_BUF \i_Madd__n0000_Mxor_Result<1>_Result1/LUT2_L_BUF  (
    .I(\i_Madd__n0000_Mxor_Result<1>_Result1/O ),
    .O(i__n0000[1])
  );
  defparam \i_Madd__n0000_Mxor_Result<1>_Result1 .INIT = 4'h6;
  X_LUT2 \i_Madd__n0000_Mxor_Result<1>_Result1  (
    .ADR0(i[0]),
    .ADR1(i[1]),
    .O(\i_Madd__n0000_Mxor_Result<1>_Result1/O )
  );
  X_CKBUF \f_BUFGP/BUFG  (
    .I(\f_BUFGP/IBUFG ),
    .O(f_BUFGP)
  );
  X_CKBUF \f_BUFGP/IBUFG_7  (
    .I(f),
    .O(\f_BUFGP/IBUFG )
  );
  X_TRI \f4t_OBUF.GTS.TRI_8  (
    .I(\f4t_OBUF.GTS.TRI ),
    .CTL(\NlwInverterSignal_f4t_OBUF.GTS.TRI/CTL ),
    .O(f4t)
  );
  X_TRI \f5t_OBUF.GTS.TRI_9  (
    .I(\f5t_OBUF.GTS.TRI ),
    .CTL(\NlwInverterSignal_f5t_OBUF.GTS.TRI/CTL ),
    .O(f5t)
  );
  X_ONE NlwBlock_fen_VCC (
    .O(VCC)
  );
  X_ZERO NlwBlock_fen_GND (
    .O(GND)
  );
  X_INV \NlwInverterBlock_f4t_OBUF.GTS.TRI/CTL  (
    .I(GTS),
    .O(\NlwInverterSignal_f4t_OBUF.GTS.TRI/CTL )
  );
  X_INV \NlwInverterBlock_f5t_OBUF.GTS.TRI/CTL  (
    .I(GTS),
    .O(\NlwInverterSignal_f5t_OBUF.GTS.TRI/CTL )
  );
endmodule