_primary.vhd

来自「verilog」· VHDL 代码 · 共 11 行

library verilog;
use verilog.vl_types.all;
entity fen is
    port(
        reset           : in     vl_logic;
        f               : in     vl_logic;
        f4t             : out    vl_logic;
        f5t             : out    vl_logic
    );
end fen;