__projnav.log

verilog

Project Navigator Auto-Make Log File
-------------------------------------


Started process "Map".

Using target part "2s50pq208-6".
ERROR:MapLib:93 - Illegal LOC on IPAD symbol "f" or BUFGP symbol "f_BUFGP"
   (output signal=f_BUFGP), IPAD-IBUFG should only be LOCed to GCLKIOB site.

Error found in mapping process, exiting...
Errors found during the mapping phase.  Please see map report file for more
details.  Output files will not be written.

Design Summary
--------------
Number of errors   :   1
Number of warnings :   0
ERROR: MAP failed
Process "Map" did not complete.

Mapping Module fen . . .
MAP command line:
map -intstyle ise -p xc2s50-pq208-6 -cm area -pr b -k 4 -c 100 -tx off -o fen_map.ncd fen.ngd fen.pcf
Mapping Module fen: failed


Project Navigator Auto-Make Log File
-------------------------------------


Started process "Map".

Using target part "2s50pq208-6".
ERROR:MapLib:93 - Illegal LOC on IPAD symbol "f" or BUFGP symbol "f_BUFGP"
   (output signal=f_BUFGP), IPAD-IBUFG should only be LOCed to GCLKIOB site.

Error found in mapping process, exiting...
Errors found during the mapping phase.  Please see map report file for more
details.  Output files will not be written.

Design Summary
--------------
Number of errors   :   1
Number of warnings :   0
ERROR: MAP failed
Process "Map" did not complete.

Mapping Module fen . . .
MAP command line:
map -intstyle ise -p xc2s50-pq208-6 -cm area -pr b -k 4 -c 100 -tx off -o fen_map.ncd fen.ngd fen.pcf
Mapping Module fen: failed


Project Navigator Auto-Make Log File
-------------------------------------


Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd g:\file\通信asic课程设计\fen/_ngo -uc
fen.ucf -p xc2s50-pq208-6 fen.ngc fen.ngd 

Reading NGO file "G:/file/通信ASIC课程设计/fen/fen.ngc" ...
Reading component libraries for design expansion...

Annotating constraints to design from file "fen.ucf" ...

Checking timing specifications ...
Checking expanded design ...

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Total memory usage is 38260 kilobytes

Writing NGD file "fen.ngd" ...

Writing NGDBUILD log file "fen.bld"...

NGDBUILD done.
Completed process "Translate".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Generate Post-Translate Simulation Model".

INFO:NetListWriters:580 - If Verilog simulation is performed outside the ISE
   Project Navigator environment, please add $XILINX/verilog/src/glbl.v to the
   simulator compile and invocation commands in order to allow proper
   initialization of the design. If simulation is performed within Project
   Navigator, this will be taken care of automatically. For more information on
   compiling and performing Xilinx simulation, consult the online Synthesis and
   Simulation Design Guide:
   http://support.xilinx.com/support/software_manuals.htm 
Completed process "Generate Post-Translate Simulation Model".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Generate Post-Translate Simulation Model".

INFO:NetListWriters:580 - If Verilog simulation is performed outside the ISE
   Project Navigator environment, please add $XILINX/verilog/src/glbl.v to the
   simulator compile and invocation commands in order to allow proper
   initialization of the design. If simulation is performed within Project
   Navigator, this will be taken care of automatically. For more information on
   compiling and performing Xilinx simulation, consult the online Synthesis and
   Simulation Design Guide:
   http://support.xilinx.com/support/software_manuals.htm 
Completed process "Generate Post-Translate Simulation Model".




Project Navigator Auto-Make Log File
-------------------------------------


Started process "Map".

Using target part "2s50pq208-6".
ERROR:MapLib:93 - Illegal LOC on IPAD symbol "f" or BUFGP symbol "f_BUFGP"
   (output signal=f_BUFGP), IPAD-IBUFG should only be LOCed to GCLKIOB site.

Error found in mapping process, exiting...
Errors found during the mapping phase.  Please see map report file for more
details.  Output files will not be written.

Design Summary
--------------
Number of errors   :   1
Number of warnings :   0
ERROR: MAP failed
Process "Map" did not complete.

Mapping Module fen . . .
MAP command line:
map -intstyle ise -p xc2s50-pq208-6 -cm area -pr b -k 4 -c 100 -tx off -o fen_map.ncd fen.ngd fen.pcf
Mapping Module fen: failed


Project Navigator Auto-Make Log File
-------------------------------------


Started process "Map".

Using target part "2s50pq208-6".
ERROR:MapLib:93 - Illegal LOC on IPAD symbol "f" or BUFGP symbol "f_BUFGP"
   (output signal=f_BUFGP), IPAD-IBUFG should only be LOCed to GCLKIOB site.

Error found in mapping process, exiting...
Errors found during the mapping phase.  Please see map report file for more
details.  Output files will not be written.

Design Summary
--------------
Number of errors   :   1
Number of warnings :   0
ERROR: MAP failed
Process "Map" did not complete.

Mapping Module fen . . .
MAP command line:
map -intstyle ise -p xc2s50-pq208-6 -cm area -pr b -k 4 -c 100 -tx off -o fen_map.ncd fen.ngd fen.pcf
Mapping Module fen: failed


Project Navigator Auto-Make Log File
-------------------------------------


Started process "Map".

Using target part "2s50pq208-6".
ERROR:MapLib:93 - Illegal LOC on IPAD symbol "f" or BUFGP symbol "f_BUFGP"
   (output signal=f_BUFGP), IPAD-IBUFG should only be LOCed to GCLKIOB site.

Error found in mapping process, exiting...
Errors found during the mapping phase.  Please see map report file for more
details.  Output files will not be written.

Design Summary
--------------
Number of errors   :   1
Number of warnings :   0
ERROR: MAP failed
Process "Map" did not complete.

Mapping Module fen . . .
MAP command line:
map -intstyle ise -p xc2s50-pq208-6 -cm area -pr b -k 4 -c 100 -tx off -o fen_map.ncd fen.ngd fen.pcf
Mapping Module fen: failed


Project Navigator Auto-Make Log File
-------------------------------------


Started process "Map".

Using target part "2s50pq208-6".
ERROR:MapLib:93 - Illegal LOC on IPAD symbol "f" or BUFGP symbol "f_BUFGP"
   (output signal=f_BUFGP), IPAD-IBUFG should only be LOCed to GCLKIOB site.

Error found in mapping process, exiting...
Errors found during the mapping phase.  Please see map report file for more
details.  Output files will not be written.

Design Summary
--------------
Number of errors   :   1
Number of warnings :   0
ERROR: MAP failed
Process "Map" did not complete.

Mapping Module fen . . .
MAP command line:
map -intstyle ise -p xc2s50-pq208-6 -cm area -pr b -k 4 -c 100 -tx off -o fen_map.ncd fen.ngd fen.pcf
Mapping Module fen: failed


Project Navigator Auto-Make Log File
-------------------------------------


Started process "Map".

Using target part "2s50pq208-6".
ERROR:MapLib:93 - Illegal LOC on IPAD symbol "f" or BUFGP symbol "f_BUFGP"
   (output signal=f_BUFGP), IPAD-IBUFG should only be LOCed to GCLKIOB site.

Error found in mapping process, exiting...
Errors found during the mapping phase.  Please see map report file for more
details.  Output files will not be written.

Design Summary
--------------
Number of errors   :   1
Number of warnings :   0
ERROR: MAP failed
Process "Map" did not complete.

Mapping Module fen . . .
MAP command line:
map -intstyle ise -p xc2s50-pq208-6 -cm area -pr b -k 4 -c 100 -tx off -o fen_map.ncd fen.ngd fen.pcf
Mapping Module fen: failed


Project Navigator Auto-Make Log File
-------------------------------------


Started process "Map".

Using target part "2s50pq208-6".
ERROR:MapLib:93 - Illegal LOC on IPAD symbol "f" or BUFGP symbol "f_BUFGP"
   (output signal=f_BUFGP), IPAD-IBUFG should only be LOCed to GCLKIOB site.

Error found in mapping process, exiting...
Errors found during the mapping phase.  Please see map report file for more
details.  Output files will not be written.

Design Summary
--------------
Number of errors   :   1
Number of warnings :   0
ERROR: MAP failed
Process "Map" did not complete.

Mapping Module fen . . .
MAP command line:
map -intstyle ise -p xc2s50-pq208-6 -cm area -pr b -k 4 -c 100 -tx off -o fen_map.ncd fen.ngd fen.pcf
Mapping Module fen: failed


Project Navigator Auto-Make Log File
-------------------------------------


Started process "Map".

Using target part "2s50pq208-6".
ERROR:MapLib:93 - Illegal LOC on IPAD symbol "f" or BUFGP symbol "f_BUFGP"
   (output signal=f_BUFGP), IPAD-IBUFG should only be LOCed to GCLKIOB site.

Error found in mapping process, exiting...
Errors found during the mapping phase.  Please see map report file for more
details.  Output files will not be written.

Design Summary
--------------
Number of errors   :   1
Number of warnings :   0
ERROR: MAP failed
Process "Map" did not complete.

Mapping Module fen . . .
MAP command line:
map -intstyle ise -p xc2s50-pq208-6 -cm area -pr b -k 4 -c 100 -tx off -o fen_map.ncd fen.ngd fen.pcf
Mapping Module fen: failed


Project Navigator Auto-Make Log File
-------------------------------------


Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd g:\file\通信asic课程设计\fen/_ngo -uc
fen.ucf -p xc2s50-pq208-6 fen.ngc fen.ngd 

Reading NGO file "G:/file/通信ASIC课程设计/fen/fen.ngc" ...
Reading component libraries for design expansion...

Annotating constraints to design from file "fen.ucf" ...

Checking timing specifications ...
Checking expanded design ...

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Total memory usage is 38260 kilobytes

Writing NGD file "fen.ngd" ...

Writing NGDBUILD log file "fen.bld"...

NGDBUILD done.
Completed process "Translate".



Started process "Map".

Using target part "2s50pq208-6".
Removing unused or disabled logic...
Running cover...
Running directed packing...
Running delay-based LUT packing...
Running related packing...

Design Summary:
Number of errors:      0
Number of warnings:    0
Logic Utilization:
  Number of Slice Flip Flops:         8 out of  1,536    1%
  Number of 4 input LUTs:             8 out of  1,536    1%
Logic Distribution:
    Number of occupied Slices:                           5 out of    768    1%
    Number of Slices containing only related logic:      5 out of      5  100%
    Number of Slices containing unrelated logic:         0 out of      5    0%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number of 4 input LUTs:         8 out of  1,536    1%
   Number of bonded IOBs:             3 out of    140    2%
   Number of GCLKs:                   1 out of      4   25%
   Number of GCLKIOBs:                1 out of      4   25%

Total equivalent gate count for design:  112
Additional JTAG gate count for IOBs:  192
Peak Memory Usage:  56 MB

NOTES:

   Related logic is defined as being logic that shares connectivity -
   e.g. two LUTs are "related" if they share common inputs.
   When assembling slices, Map gives priority to combine logic that
   is related.  Doing so results in the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin
   packing unrelated logic into a slice once 99% of the slices are
   occupied through related logic packing.

   Note that once logic distribution reaches the 99% level through
   related logic packing, this does not mean the device is completely
   utilized.  Unrelated logic packing will then begin, continuing until
   all usable LUTs and FFs are occupied.  Depending on your timing
   budget, increased levels of unrelated logic packing may adversely
   affect the overall timing performance of your design.


Mapping completed.
See MAP report file "fen_map.mrp" for details.
Completed process "Map".

Mapping Module fen . . .
MAP command line:
map -intstyle ise -p xc2s50-pq208-6 -cm area -pr b -k 4 -c 100 -tx off -o fen_map.ncd fen.ngd fen.pcf
Mapping Module fen: DONE



Started process "Place & Route".





Constraints file: fen.pcf

Loading device database for application Par from file "fen_map.ncd".
   "fen" is an NCD, version 2.38, device xc2s50, package pq208, speed -6
Loading device for application Par from file 'v50.nph' in environment E:/Xilinx.
Device speed data version:  PRODUCTION 1.27 2003-06-19.


Resolving physical constraints.
Finished resolving physical constraints.

Device utilization summary:

   Number of External GCLKIOBs         1 out of 4      25%
   Number of External IOBs             3 out of 140     2%
      Number of LOCed External IOBs    3 out of 3     100%

   Number of SLICEs                    5 out of 768     1%

   Number of GCLKs                     1 out of 4      25%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Phase 1.1
Phase 1.1 (Checksum:9896a7) REAL time: 0 secs 

Phase 2.23
Phase 2.23 (Checksum:1312cfe) REAL time: 0 secs 

Phase 3.3
Phase 3.3 (Checksum:1c9c37d) REAL time: 0 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 0 secs 

Phase 5.8
.
Phase 5.8 (Checksum:98b911) REAL time: 0 secs 

Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 0 secs 

Phase 7.18
Phase 7.18 (Checksum:42c1d79) REAL time: 0 secs 

Writing design to file fen.ncd.

Total REAL time to Placer completion: 0 secs 
Total CPU time to Placer completion: 0 secs 


Phase 1: 40 unrouted;       REAL time: 0 secs 

Phase 2: 35 unrouted;       REAL time: 0 secs 

Phase 3: 12 unrouted;       REAL time: 0 secs 

Phase 4: 0 unrouted;       REAL time: 0 secs 

Total REAL time to Router completion: 0 secs 
Total CPU time to Router completion: 0 secs 

Generating "par" statistics.

**************************
Generating Clock Report
**************************

+----------------------------+----------+--------+------------+-------------+
|         Clock Net          | Resource | Fanout |Net Skew(ns)|Max Delay(ns)|
+----------------------------+----------+--------+------------+-------------+
|           f_BUFGP          |  Global  |    5   |  0.005     |  0.394      |
+----------------------------+----------+--------+------------+-------------+

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 0 secs 
Total CPU time to PAR completion: 0 secs 

Peak Memory Usage:  45 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Writing design to file fen.ncd.


PAR done.
Completed process "Place & Route".


Started process "Generate Post-Place & Route Static Timing".


Analysis completed Sat Mar 05 15:36:01 2005
--------------------------------------------------------------------------------

Generating Report ...

Completed process "Generate Post-Place & Route Static Timing".

Place & Route Module fen . . .
PAR command line: par -w -intstyle ise -ol std -t 1 fen_map.ncd fen.ncd fen.pcf
PAR completed successfully