fen.syr

verilog

Release 6.1i - xst G.23
Copyright (c) 1995-2003 Xilinx, Inc.  All rights reserved.
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--> Reading design: fen.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
     4.1) HDL Synthesis Report
  5) Advanced HDL Synthesis
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : fen.prj
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO
Verilog Include Directory          : 

---- Target Parameters
Output File Name                   : fen
Output Format                      : NGC
Target Device                      : xc2s50-6-pq208

---- Source Options
Top Module Name                    : fen
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Multiplier Style                   : lut
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 100
Add Generic Clock Buffer(BUFG)     : 4
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : _
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : fen.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
Optimize Instantiated Primitives   : NO

=========================================================================

WARNING:Xst:1885 - LSO file is empty, default list of libraries is used

=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "fen.v"
Module <fen> compiled
No errors in compilation
Analysis of file <fen.prj> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <fen>.
Module <fen> is correct for synthesis.
 

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <fen>.
    Related source file is fen.v.
    Found 1-bit register for signal <f4t>.
    Found 1-bit register for signal <f5t>.
    Found 3-bit adder for signal <$n0012> created at line 56.
    Found 3-bit up counter for signal <i>.
    Found 3-bit register for signal <j>.
    Found 2 1-bit 2-to-1 multiplexers.
    Summary:
	inferred   1 Counter(s).
	inferred   5 D-type flip-flop(s).
	inferred   1 Adder/Subtracter(s).
	inferred   2 Multiplexer(s).
Unit <fen> synthesized.


=========================================================================
HDL Synthesis Report

Macro Statistics
# Registers                        : 3
  1-bit register                   : 2
  3-bit register                   : 1
# Counters                         : 1
  3-bit up counter                 : 1
# Multiplexers                     : 2
  2-to-1 multiplexer               : 2
# Adders/Subtractors               : 1
  3-bit adder                      : 1

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================


=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <fen> ...
Loading device for application Xst from file 'v50.nph' in environment E:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block fen, actual ratio is 0.

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : fen.ngr
Top Level Output File Name         : fen
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 4

Macro Statistics :
# Registers                        : 4
#      1-bit register              : 2
#      3-bit register              : 2
# Multiplexers                     : 2
#      2-to-1 multiplexer          : 2

Cell Usage :
# BELS                             : 11
#      LUT1                        : 2
#      LUT1_L                      : 1
#      LUT2_L                      : 2
#      LUT3_L                      : 4
#      LUT4_D                      : 1
#      LUT4_L                      : 1
# FlipFlops/Latches                : 8
#      FDR                         : 7
#      FDRE                        : 1
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 3
#      IBUF                        : 1
#      OBUF                        : 2
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s50pq208-6 

 Number of Slices:                       6  out of    768     0%  
 Number of Slice Flip Flops:             8  out of   1536     0%  
 Number of 4 input LUTs:                11  out of   1536     0%  
 Number of bonded IOBs:                  3  out of    144     2%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
f                                  | BUFGP                  | 8     |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 5.140ns (Maximum Frequency: 194.553MHz)
   Minimum input arrival time before clock: 4.831ns
   Maximum output required time after clock: 6.959ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'f'
Delay:               5.140ns (Levels of Logic = 1)
  Source:            i_0 (FF)
  Destination:       i_1 (FF)
  Source Clock:      f rising
  Destination Clock: f rising

  Data Path: i_0 to i_1
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q              5   1.085   1.566  i_0 (i_0)
     LUT4_D:I0->O          2   0.549   1.206  _n00021 (_n0002)
     FDR:R                     0.734          i_2
    ----------------------------------------
    Total                      5.140ns (2.368ns logic, 2.772ns route)
                                       (46.1% logic, 53.9% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock 'f'
Offset:              4.831ns (Levels of Logic = 2)
  Source:            reset (PAD)
  Destination:       j_1 (FF)
  Destination Clock: f rising

  Data Path: reset to j_1
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             2   0.776   1.206  reset_IBUF (reset_IBUF)
     LUT1:I0->O            5   0.549   1.566  f4t_N551 (f4t_N55)
     FDRE:R                    0.734          f4t
    ----------------------------------------
    Total                      4.831ns (2.059ns logic, 2.772ns route)
                                       (42.6% logic, 57.4% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'f'
Offset:              6.959ns (Levels of Logic = 1)
  Source:            f4t (FF)
  Destination:       f4t (PAD)
  Source Clock:      f rising

  Data Path: f4t to f4t
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDRE:C->Q             2   1.085   1.206  f4t (f4t_OBUF)
     OBUF:I->O                 4.668          f4t_OBUF (f4t)
    ----------------------------------------
    Total                      6.959ns (5.753ns logic, 1.206ns route)
                                       (82.7% logic, 17.3% route)

=========================================================================
CPU : 0.88 / 1.23 s | Elapsed : 1.00 / 2.00 s
 
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Total memory usage is 54472 kilobytes