fen.gfl

verilog

ProjNav -> New -> Test Fixture
__projnav/createTF.err
# ModelSim : Simulate Behavioral Verilog Model
fen_fen_test_v_tf.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# XST (Creating Lso File) : 
fen.lso
# xst flow : RunXST
fen.syr
fen.prj
fen.sprj
fen.ana
fen.stx
fen.cmd_log
fen.ngc
fen.ngr
# Edit Constraints (Text)
__projnav/parentEditConstraintsTextApp_tcl.rsp
# Implmentation : Translate
__projnav/ngdbuild.err
__projnav/ednTOngd_tcl.rsp
g:\file\通信asic课程设计\fen/_ngo
fen.ngd
fen_ngdbuild.nav
fen.bld
.untf
fen.cmd_log
# Assign Package Pins
__projnav/parentAssignPackagePinsApp_tcl.rsp
# Implmentation : Translate
__projnav/ngdbuild.err
__projnav/ednTOngd_tcl.rsp
g:\file\通信asic课程设计\fen/_ngo
fen.ngd
fen_ngdbuild.nav
fen.bld
fen.ucf.untf
fen.cmd_log
# Implementation : Map
fen_map.ncd
fen.ngm
fen.pcf
fen.nc1
fen.mrp
fen_map.mrp
fen.mdf
__projnav/map.log
fen.cmd_log
MAP_NO_GUIDE_FILE_CPF "fen"
# Implmentation : Post-Place & Route Timing
__projnav/ncdTOtwr_tcl.rsp
__projnav/posttrc.log
fen.twr
fen.twx
fen.tsi
fen.cmd_log
# Implmentation : Place & Route
__projnav/nc1TOncd_tcl.rsp
fen.ncd
fen.par
fen.pad
fen_pad.txt
fen_pad.csv
fen.pad_txt
fen.dly
reportgen.log
fen.xpi
fen.grf
fen.itr
fen_last_par.ncd
__projnav/par.log
fen.placed_ncd_tracker
fen.routed_ncd_tracker
fen.cmd_log
PAR_NO_GUIDE_FILE_CPF "fen"
# Generate Programming File
__projnav/fen_ncdTOut_tcl.rsp
__projnav/bitgen.rsp
bitgen.ut
fen.ut
# Generate Programming File
fen.bgn
fen.rbt
fen.ll
fen.msk
fen.drc
fen.nky
fen.bit
fen.bin
fen.isc
fen.cmd_log
# Generate PROM, ACE, or JTAG File
fen.ace
xilinx.sys
fen.mpm
fen.mcs
fen.prm
fen.dst
fen.exo
fen.tek
fen.hex
fen.svf
fen.stapl
impact.cmd
_impact.log
_impact.cmd
# Generate PROM, ACE, or JTAG File
fen.ace
xilinx.sys
fen.mpm
fen.mcs
fen.prm
fen.dst
fen.exo
fen.tek
fen.hex
fen.svf
fen.stapl
impact.cmd
_impact.log
_impact.cmd
# Assign Package Pins
__projnav/parentAssignPackagePinsApp_tcl.rsp
# Implmentation : Translate
__projnav/ngdbuild.err
__projnav/ednTOngd_tcl.rsp
g:\file\通信asic课程设计\fen/_ngo
fen.ngd
fen_ngdbuild.nav
fen.bld
fen.ucf.untf
fen.cmd_log
# Implementation : Map
fen_map.ncd
fen.ngm
fen.pcf
fen.nc1
fen.mrp
fen_map.mrp
fen.mdf
__projnav/map.log
fen.cmd_log
MAP_NO_GUIDE_FILE_CPF "fen"
# Implementation : Map
fen_map.ncd
fen.ngm
fen.pcf
fen.nc1
fen.mrp
fen_map.mrp
fen.mdf
__projnav/map.log
fen.cmd_log
MAP_NO_GUIDE_FILE_CPF "fen"
# Implmentation : Translate
__projnav/ngdbuild.err
__projnav/ednTOngd_tcl.rsp
g:\file\通信asic课程设计\fen/_ngo
fen.ngd
fen_ngdbuild.nav
fen.bld
fen.ucf.untf
fen.cmd_log
# Implementation : Map
fen_map.ncd
fen.ngm
fen.pcf
fen.nc1
fen.mrp
fen_map.mrp
fen.mdf
__projnav/map.log
fen.cmd_log
MAP_NO_GUIDE_FILE_CPF "fen"
# Assign Package Pins
__projnav/parentAssignPackagePinsApp_tcl.rsp
# Implementation : Map
fen_map.ncd
fen.ngm
fen.pcf
fen.nc1
fen.mrp
fen_map.mrp
fen.mdf
__projnav/map.log
fen.cmd_log
MAP_NO_GUIDE_FILE_CPF "fen"
# Assign Package Pins
__projnav/parentAssignPackagePinsApp_tcl.rsp
# Implementation : Map
fen_map.ncd
fen.ngm
fen.pcf
fen.nc1
fen.mrp
fen_map.mrp
fen.mdf
__projnav/map.log
fen.cmd_log
MAP_NO_GUIDE_FILE_CPF "fen"
# Assign Package Pins
__projnav/parentAssignPackagePinsApp_tcl.rsp
# Implmentation : Translate
__projnav/ngdbuild.err
__projnav/ednTOngd_tcl.rsp
g:\file\通信asic课程设计\fen/_ngo
fen.ngd
fen_ngdbuild.nav
fen.bld
fen.ucf.untf
fen.cmd_log
# Implementation : Generate Post-Translate Simulation Model
fen_translate.v
fen_translate.v
fen_translate.nlf
fen.xlate_nlf
fen.xlate_nlf
fen.cmd_log
# Implementation : Generate Post-Translate Simulation Model
fen_translate.v
fen_translate.v
fen_translate.nlf
fen.xlate_nlf
fen.versim_xlate
fen.cmd_log
# ModelSim : Simulate Post-Translate VHDL Model
fen_fen_test_v_tf.ndo
# ModelSim : Simulate Post-Translate Verilog Model
vsim.wlf
# Implementation : Map
fen_map.ncd
fen.ngm
fen.pcf
fen.nc1
fen.mrp
fen_map.mrp
fen.mdf
__projnav/map.log
fen.cmd_log
MAP_NO_GUIDE_FILE_CPF "fen"
# Implementation : Map
fen_map.ncd
fen.ngm
fen.pcf
fen.nc1
fen.mrp
fen_map.mrp
fen.mdf
__projnav/map.log
fen.cmd_log
MAP_NO_GUIDE_FILE_CPF "fen"
# Create Area Constraints
__projnav/parentCreateAreaConstraintsApp_tcl.rsp
# Edit Constraints (Text)
__projnav/parentEditConstraintsTextApp_tcl.rsp
# Implementation : Map
fen_map.ncd
fen.ngm
fen.pcf
fen.nc1
fen.mrp
fen_map.mrp
fen.mdf
__projnav/map.log
fen.cmd_log
MAP_NO_GUIDE_FILE_CPF "fen"
# Implementation : Map
fen_map.ncd
fen.ngm
fen.pcf
fen.nc1
fen.mrp
fen_map.mrp
fen.mdf
__projnav/map.log
fen.cmd_log
MAP_NO_GUIDE_FILE_CPF "fen"
# Implmentation : Floorplan Design
__projnav/xlateFloorPlanner.rsp
# Implementation : Map
fen_map.ncd
fen.ngm
fen.pcf
fen.nc1
fen.mrp
fen_map.mrp
fen.mdf
__projnav/map.log
fen.cmd_log
MAP_NO_GUIDE_FILE_CPF "fen"
# Assign Package Pins Post-Translate
__projnav/xlatePace.rsp
# Implementation : Map
fen_map.ncd
fen.ngm
fen.pcf
fen.nc1
fen.mrp
fen_map.mrp
fen.mdf
__projnav/map.log
fen.cmd_log
MAP_NO_GUIDE_FILE_CPF "fen"
# Edit Constraints (Text)
__projnav/parentEditConstraintsTextApp_tcl.rsp
# Implementation : Map
fen_map.ncd
fen.ngm
fen.pcf
fen.nc1
fen.mrp
fen_map.mrp
fen.mdf
__projnav/map.log
fen.cmd_log
MAP_NO_GUIDE_FILE_CPF "fen"
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# Edit Constraints (Text)
__projnav/parentEditConstraintsTextApp_tcl.rsp
# Implmentation : Translate
__projnav/ngdbuild.err
__projnav/ednTOngd_tcl.rsp
g:\file\通信asic课程设计\fen/_ngo
fen.ngd
fen_ngdbuild.nav
fen.bld
fen.ucf.untf
fen.cmd_log
# Implementation : Map
fen_map.ncd
fen.ngm
fen.pcf
fen.nc1
fen.mrp
fen_map.mrp
fen.mdf
__projnav/map.log
fen.cmd_log
MAP_NO_GUIDE_FILE_CPF "fen"
# Implmentation : Post-Place & Route Timing
__projnav/ncdTOtwr_tcl.rsp
__projnav/posttrc.log
fen.twr
fen.twx
fen.tsi
fen.cmd_log
# Implmentation : Place & Route
__projnav/nc1TOncd_tcl.rsp
fen.ncd
fen.par
fen.pad
fen_pad.txt
fen_pad.csv
fen.pad_txt
fen.dly
reportgen.log
fen.xpi
fen.grf
fen.itr
fen_last_par.ncd
__projnav/par.log
fen.placed_ncd_tracker
fen.routed_ncd_tracker
fen.cmd_log
PAR_NO_GUIDE_FILE_CPF "fen"
# Implementation : Generate Post-Translate Simulation Model
fen_translate.v
fen_translate.v
fen_translate.nlf
fen.xlate_nlf
fen.versim_xlate
fen.cmd_log
# Generate Programming File
__projnav/fen_ncdTOut_tcl.rsp
__projnav/bitgen.rsp
bitgen.ut
fen.ut
# Generate Programming File
fen.bgn
fen.rbt
fen.ll
fen.msk
fen.drc
fen.nky
fen.bit
fen.bin
fen.isc
fen.cmd_log
# Generate PROM, ACE, or JTAG File
fen.ace
xilinx.sys
fen.mpm
fen.mcs
fen.prm
fen.dst
fen.exo
fen.tek
fen.hex
fen.svf
fen.stapl
impact.cmd
_impact.log
_impact.cmd
# Generate PROM, ACE, or JTAG File
fen.ace
xilinx.sys
fen.mpm
fen.mcs
fen.prm
fen.dst
fen.exo
fen.tek
fen.hex
fen.svf
fen.stapl
impact.cmd
_impact.log
_impact.cmd
# Assign Package Pins
__projnav/parentAssignPackagePinsApp_tcl.rsp
# ModelSim : Simulate Post-Translate VHDL Model
fen_fen_test_v_tf.ndo
# ModelSim : Simulate Post-Translate Verilog Model
vsim.wlf
# Implementation : Generate Post-Map Simulation Model
fen_map.v
SimModelBaseName.sdf
fen_map.sdf
fen_map.v
fen_map.nlf
fen.map_nlf
fen.versim_map
fen.cmd_log
__projnav/netgen_map_tcl.rsp
# ModelSim : Simulate Post-Map VHDL Model
fen_fen_test_v_tf.mdo
# ModelSim : Simulate Post-Map Verilog Model
vsim.wlf
# Implementation : Generate Post-Par Simulation Model
fen_timesim.v
fen_timesim.sdf
fen_timesim.sdf
fen_timesim.v
fen_timesim.nlf
fen.par_nlf
fen.versim_par
fen.cmd_log
__projnav/netgen_par_tcl.rsp
# ModelSim : Simulate Post-Place & Route VHDL Model
fen_fen_test_v_tf.tdo
# ModelSim : Simulate Post-Place & Route Verilog Model
vsim.wlf
# Assign Package Pins
__projnav/parentAssignPackagePinsApp_tcl.rsp
# Implmentation : Translate
__projnav/ngdbuild.err
__projnav/ednTOngd_tcl.rsp
g:\file\通信asic课程设计\fen/_ngo
fen.ngd
fen_ngdbuild.nav
fen.bld
fen.ucf.untf
fen.cmd_log
# Implementation : Map
fen_map.ncd
fen.ngm
fen.pcf
fen.nc1
fen.mrp
fen_map.mrp
fen.mdf
__projnav/map.log
fen.cmd_log
MAP_NO_GUIDE_FILE_CPF "fen"
# Implmentation : Post-Place & Route Timing
__projnav/ncdTOtwr_tcl.rsp
__projnav/posttrc.log
fen.twr
fen.twx
fen.tsi
fen.cmd_log
# Implmentation : Place & Route
__projnav/nc1TOncd_tcl.rsp
fen.ncd
fen.par
fen.pad
fen_pad.txt
fen_pad.csv
fen.pad_txt
fen.dly
reportgen.log
fen.xpi
fen.grf
fen.itr
fen_last_par.ncd
__projnav/par.log
fen.placed_ncd_tracker
fen.routed_ncd_tracker
fen.cmd_log
PAR_NO_GUIDE_FILE_CPF "fen"
# Generate Programming File
__projnav/fen_ncdTOut_tcl.rsp
__projnav/bitgen.rsp
bitgen.ut
fen.ut
# Generate Programming File
fen.bgn
fen.rbt
fen.ll
fen.msk
fen.drc
fen.nky
fen.bit
fen.bin
fen.isc
fen.cmd_log
# Generate PROM, ACE, or JTAG File
fen.ace
xilinx.sys
fen.mpm
fen.mcs
fen.prm
fen.dst
fen.exo
fen.tek
fen.hex
fen.svf
fen.stapl
impact.cmd
_impact.log
_impact.cmd
# Edit Constraints (Text)
__projnav/parentEditConstraintsTextApp_tcl.rsp
# Implmentation : Translate
__projnav/ngdbuild.err
__projnav/ednTOngd_tcl.rsp
g:\file\通信asic课程设计\fen/_ngo
fen.ngd
fen_ngdbuild.nav
fen.bld
fen.ucf.untf
fen.cmd_log
# Implementation : Map
fen_map.ncd
fen.ngm
fen.pcf
fen.nc1
fen.mrp
fen_map.mrp
fen.mdf
__projnav/map.log
fen.cmd_log
MAP_NO_GUIDE_FILE_CPF "fen"
# Implmentation : Post-Place & Route Timing
__projnav/ncdTOtwr_tcl.rsp
__projnav/posttrc.log
fen.twr
fen.twx
fen.tsi
fen.cmd_log
# Implmentation : Place & Route
__projnav/nc1TOncd_tcl.rsp
fen.ncd
fen.par
fen.pad
fen_pad.txt
fen_pad.csv
fen.pad_txt
fen.dly
reportgen.log
fen.xpi
fen.grf
fen.itr
fen_last_par.ncd
__projnav/par.log
fen.placed_ncd_tracker
fen.routed_ncd_tracker
fen.cmd_log
PAR_NO_GUIDE_FILE_CPF "fen"
# Generate Programming File
__projnav/fen_ncdTOut_tcl.rsp
__projnav/bitgen.rsp
bitgen.ut
fen.ut
# Generate Programming File
fen.bgn
fen.rbt
fen.ll
fen.msk
fen.drc
fen.nky
fen.bit
fen.bin
fen.isc
fen.cmd_log
# Generate PROM, ACE, or JTAG File
fen.ace
xilinx.sys
fen.mpm
fen.mcs
fen.prm
fen.dst
fen.exo
fen.tek
fen.hex
fen.svf
fen.stapl
impact.cmd
_impact.log
_impact.cmd
# Assign Package Pins
__projnav/parentAssignPackagePinsApp_tcl.rsp
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf