fen_test.v

verilog

`timescale 1ns/100ps
`define clk_cycle 10


module fen_fen_test_v_tf();

// DATE:     11:00:19 03/05/2005 
// MODULE:   fen
// DESIGN:   fen
// FILENAME: fen_test.v
// PROJECT:  fen
// VERSION:  


// Inputs
    reg reset;
    reg f;


// Outputs
    wire f4t;
    wire f5t;


    always #`clk_cycle f=~f;

    initial
      begin
	   reset=1;
	   f=0;
	   #10 reset=0;
	   #25 reset=1;
	   #10000 $stop;
	 end


// Instantiate the UUT
    fen uut (
        .reset(reset), 
        .f(f), 
        .f4t(f4t), 
        .f5t(f5t)
        );


// Initialize Inputs
    `ifdef auto_init

        initial begin
            reset = 0;
            f = 0;
        end

    `endif


endmodule