fen_map.v

verilog

// Xilinx Verilog netlist produced by netgen application (version G.23)
// Command      : -intstyle ise -s 6 -pcf fen.pcf -ngm fen.ngm -w -ofmt verilog -sim fen_map.ncd fen_map.v 
// Input file   : fen_map.ncd
// Output file  : fen_map.v
// Design name  : fen
// # of Modules : 1
// Xilinx       : E:/Xilinx
// Device       : 2s50pq208-6 (PRODUCTION 1.27 2003-06-19)

// This verilog netlist is a simulation model and uses simulation 
// primitives which may not represent the true implementation of the 
// device, however the netlist is functionally correct and should not 
// be modified. This file cannot be synthesized and should only be used 
// with supported simulation tools.

`timescale 1 ns/1 ps

module fen (
  f5t, f4t, f, reset
);
  output f5t;
  output f4t;
  input f;
  input reset;
  wire \f_BUFGP/IBUFG ;
  wire f4t_OBUF;
  wire f5t_OBUF;
  wire reset_IBUF;
  wire f_BUFGP;
  wire \_n00001/O ;
  wire _n0002;
  wire GSR = glbl.GSR;
  wire GTS = glbl.GTS;
  wire \f4t/ENABLE ;
  wire \f4t/TORGTS ;
  wire \f4t/OUTMUX ;
  wire \f5t/ENABLE ;
  wire \f5t/TORGTS ;
  wire \f5t/OUTMUX ;
  wire \reset/IBUF ;
  wire \f4t_OBUF/GROM ;
  wire \f4t_OBUF/SRMUX_OUTPUTNOT ;
  wire \f4t_OBUF/BYMUXNOT ;
  wire \_n0004<2>1/O ;
  wire \j<2>/SRMUX_OUTPUTNOT ;
  wire \Mmux__n0003_Result1/O ;
  wire \i_Madd__n0000_Mxor_Result<1>_Result1/O ;
  wire \i<1>/GROM ;
  wire \i<1>/BYMUXNOT ;
  wire \i_Madd__n0000_Mxor_Result<2>_Result1/O ;
  wire \_n0004<1>1/O ;
  wire \j<1>/SRMUX_OUTPUTNOT ;
  wire \_n0004<0>1/O ;
  wire \f_BUFGP/BUFG/CE ;
  wire VCC;
  wire GND;
  wire [2 : 0] i;
  wire [2 : 0] j;
  initial $sdf_annotate("fen_map.sdf");
  X_OPAD \f4t/PAD  (
    .PAD(f4t)
  );
  X_TRI f4t_OBUF_0 (
    .I(\f4t/OUTMUX ),
    .CTL(\f4t/ENABLE ),
    .O(f4t)
  );
  X_INV \f4t/ENABLEINV  (
    .I(\f4t/TORGTS ),
    .O(\f4t/ENABLE )
  );
  X_BUF \f4t/GTS_OR  (
    .I(GTS),
    .O(\f4t/TORGTS )
  );
  X_BUF \f4t/OUTMUX_1  (
    .I(f4t_OBUF),
    .O(\f4t/OUTMUX )
  );
  X_OPAD \f5t/PAD  (
    .PAD(f5t)
  );
  X_TRI f5t_OBUF_2 (
    .I(\f5t/OUTMUX ),
    .CTL(\f5t/ENABLE ),
    .O(f5t)
  );
  X_INV \f5t/ENABLEINV  (
    .I(\f5t/TORGTS ),
    .O(\f5t/ENABLE )
  );
  X_BUF \f5t/GTS_OR  (
    .I(GTS),
    .O(\f5t/TORGTS )
  );
  X_BUF \f5t/OUTMUX_3  (
    .I(f5t_OBUF),
    .O(\f5t/OUTMUX )
  );
  X_IPAD \reset/PAD  (
    .PAD(reset)
  );
  X_BUF \reset/IMUX  (
    .I(\reset/IBUF ),
    .O(reset_IBUF)
  );
  X_BUF reset_IBUF_4 (
    .I(reset),
    .O(\reset/IBUF )
  );
  defparam _n00001.INIT = 16'h0404;
  X_LUT4 _n00001 (
    .ADR0(i[2]),
    .ADR1(i[0]),
    .ADR2(i[1]),
    .ADR3(VCC),
    .O(\f4t_OBUF/GROM )
  );
  X_BUF \f4t_OBUF/YUSED  (
    .I(\f4t_OBUF/GROM ),
    .O(\_n00001/O )
  );
  X_INV \f4t_OBUF/BYMUX  (
    .I(f4t_OBUF),
    .O(\f4t_OBUF/BYMUXNOT )
  );
  X_INV \f4t_OBUF/SRMUX  (
    .I(reset_IBUF),
    .O(\f4t_OBUF/SRMUX_OUTPUTNOT )
  );
  defparam \_n0004<2>1 .INIT = 16'h6868;
  X_LUT4 \_n0004<2>1  (
    .ADR0(j[1]),
    .ADR1(j[0]),
    .ADR2(j[2]),
    .ADR3(VCC),
    .O(\_n0004<2>1/O )
  );
  defparam Mmux__n0003_Result1.INIT = 16'hAA96;
  X_LUT4 Mmux__n0003_Result1 (
    .ADR0(f5t_OBUF),
    .ADR1(j[2]),
    .ADR2(j[0]),
    .ADR3(j[1]),
    .O(\Mmux__n0003_Result1/O )
  );
  X_INV \j<2>/SRMUX  (
    .I(reset_IBUF),
    .O(\j<2>/SRMUX_OUTPUTNOT )
  );
  defparam \i_Madd__n0000_Mxor_Result<1>_Result1 .INIT = 16'h6666;
  X_LUT4 \i_Madd__n0000_Mxor_Result<1>_Result1  (
    .ADR0(i[0]),
    .ADR1(i[1]),
    .ADR2(VCC),
    .ADR3(VCC),
    .O(\i_Madd__n0000_Mxor_Result<1>_Result1/O )
  );
  defparam _n00021.INIT = 16'h02FF;
  X_LUT4 _n00021 (
    .ADR0(i[0]),
    .ADR1(i[1]),
    .ADR2(i[2]),
    .ADR3(reset_IBUF),
    .O(\i<1>/GROM )
  );
  X_BUF \i<1>/YUSED  (
    .I(\i<1>/GROM ),
    .O(_n0002)
  );
  X_INV \i<1>/BYMUX  (
    .I(i[0]),
    .O(\i<1>/BYMUXNOT )
  );
  defparam \i_Madd__n0000_Mxor_Result<2>_Result1 .INIT = 16'h6A6A;
  X_LUT4 \i_Madd__n0000_Mxor_Result<2>_Result1  (
    .ADR0(i[2]),
    .ADR1(i[0]),
    .ADR2(i[1]),
    .ADR3(VCC),
    .O(\i_Madd__n0000_Mxor_Result<2>_Result1/O )
  );
  defparam \_n0004<1>1 .INIT = 16'h6666;
  X_LUT4 \_n0004<1>1  (
    .ADR0(j[1]),
    .ADR1(j[0]),
    .ADR2(VCC),
    .ADR3(VCC),
    .O(\_n0004<1>1/O )
  );
  defparam \_n0004<0>1 .INIT = 16'h4545;
  X_LUT4 \_n0004<0>1  (
    .ADR0(j[0]),
    .ADR1(j[1]),
    .ADR2(j[2]),
    .ADR3(VCC),
    .O(\_n0004<0>1/O )
  );
  X_INV \j<1>/SRMUX  (
    .I(reset_IBUF),
    .O(\j<1>/SRMUX_OUTPUTNOT )
  );
  defparam f4t_5.INIT = 1'b0;
  X_SFF f4t_5 (
    .I(\f4t_OBUF/BYMUXNOT ),
    .CE(\_n00001/O ),
    .CLK(f_BUFGP),
    .SET(GND),
    .RST(GSR),
    .SSET(GND),
    .SRST(\f4t_OBUF/SRMUX_OUTPUTNOT ),
    .O(f4t_OBUF)
  );
  defparam f5t_6.INIT = 1'b0;
  X_SFF f5t_6 (
    .I(\Mmux__n0003_Result1/O ),
    .CE(VCC),
    .CLK(f_BUFGP),
    .SET(GND),
    .RST(GSR),
    .SSET(GND),
    .SRST(\j<2>/SRMUX_OUTPUTNOT ),
    .O(f5t_OBUF)
  );
  defparam i_0.INIT = 1'b0;
  X_SFF i_0 (
    .I(\i<1>/BYMUXNOT ),
    .CE(VCC),
    .CLK(f_BUFGP),
    .SET(GND),
    .RST(GSR),
    .SSET(GND),
    .SRST(_n0002),
    .O(i[0])
  );
  defparam j_2.INIT = 1'b0;
  X_SFF j_2 (
    .I(\_n0004<2>1/O ),
    .CE(VCC),
    .CLK(f_BUFGP),
    .SET(GND),
    .RST(GSR),
    .SSET(GND),
    .SRST(\j<2>/SRMUX_OUTPUTNOT ),
    .O(j[2])
  );
  defparam i_2.INIT = 1'b0;
  X_SFF i_2 (
    .I(\i_Madd__n0000_Mxor_Result<2>_Result1/O ),
    .CE(VCC),
    .CLK(f_BUFGP),
    .SET(GND),
    .RST(GSR),
    .SSET(GND),
    .SRST(_n0002),
    .O(i[2])
  );
  defparam i_1.INIT = 1'b0;
  X_SFF i_1 (
    .I(\i_Madd__n0000_Mxor_Result<1>_Result1/O ),
    .CE(VCC),
    .CLK(f_BUFGP),
    .SET(GND),
    .RST(GSR),
    .SSET(GND),
    .SRST(_n0002),
    .O(i[1])
  );
  defparam j_0.INIT = 1'b0;
  X_SFF j_0 (
    .I(\_n0004<0>1/O ),
    .CE(VCC),
    .CLK(f_BUFGP),
    .SET(GND),
    .RST(GSR),
    .SSET(GND),
    .SRST(\j<1>/SRMUX_OUTPUTNOT ),
    .O(j[0])
  );
  defparam j_1.INIT = 1'b0;
  X_SFF j_1 (
    .I(\_n0004<1>1/O ),
    .CE(VCC),
    .CLK(f_BUFGP),
    .SET(GND),
    .RST(GSR),
    .SSET(GND),
    .SRST(\j<1>/SRMUX_OUTPUTNOT ),
    .O(j[1])
  );
  X_IPAD \f/PAD  (
    .PAD(f)
  );
  X_CKBUF \f/BUF  (
    .I(f),
    .O(\f_BUFGP/IBUFG )
  );
  X_CKBUF \f_BUFGP/BUFG/BUF  (
    .I(\f_BUFGP/IBUFG ),
    .O(f_BUFGP)
  );
  X_ONE NlwBlock_fen_VCC (
    .O(VCC)
  );
  X_ZERO NlwBlock_fen_GND (
    .O(GND)
  );
endmodule