fen.v

verilog

module fen(reset,f,f4t,f5t);
    input reset;
    input f;
    output f4t;
    output f5t;

    reg f4t;
    reg[2:0] i;

    reg f5t;
    reg[2:0] j;


	 always @(posedge f)
      if(!reset)
	   begin
	   f4t<=0;
	   i<=0;
	   end
	 else
	   begin
	   	if(i==1)
		  begin
		    i<=0;
		    f4t<=~f4t;
		  end
          else
		  begin
		    i<=i+1;
		  end
	   end


	   always @(posedge f)
        if(!reset)
	     begin
	       f5t<=0;
		  j<=0;
	     end
	   else
	     begin
	       if(j==1)
		    begin
		      f5t<=~f5t;
		      j<=j+1;
		    end
            else
		    begin
		      if(j==4)
		        begin
			     f5t<=~f5t;
                    j<=0;
			   end
		      else
		        begin
			     j<=j+1;
			   end
		    end
	     end







endmodule