flowadd.v

verilog编写的32位浮点加法器

module flowadd(ix, iy, ze, zm, clk, a_en, ost);
   input ix, iy, clk, a_en;
   output ze, zm, ost;
   
   wire[31:0]   ix, iy;
   wire   clk, ost;
         
   //reg[31:0] z, x, y;
   reg[24:0]    xm, ym, zm;  
      //the [ c 1. m ]   incldue 1-bit reg "c" for upflow but NOT SIGN 
      //   and include 3-bit reg for downward overflow
      //   so the fragment point is before the 3th
   reg[7:0]     xe, ye, ze;   //exponent
   reg mc, ms;
   reg[2:0]	state;
   
   parameter   start =   3'b000,
               zerock =  3'b001,
               exequal = 3'b010,
               addm =    3'b011,
               infifl =  3'b100,
               zerofl =  3'b101,
               over =    3'b110,
               idle =    3'b111;
   // output state : 1 output enable, 0 unable
   assign ost = (state == over) ? 1 : 0;
   
   always@(posedge clk)
      begin 
         if(!a_en)  
         begin
            zm <= 24'bz;
            ze <= 8'bz;
         end
		 else 
//			add_tsk;
//	  end
//		 task add_tsk;
 
				casex(state)
					start:
					begin 
							xe <= ix[7:0];
							xm <= {1'b0,1'b1,ix[31:8]};
							ye <= iy[7:0];
							ym <= {1'b0,1'b1,iy[31:8]};
							state <= zerock;
					end
					zerock:  /*zero check*/
					begin 
							if(xm == 0)
								begin   
								{ze, zm} <= {ye, ym};
								state <= over;
								end
							else
								if(ym == 0)
									begin
									{ze, zm} <= {xe, xm};
									state <= over;
									end
								else
									state <= exequal;						
					end
					exequal: /*exponent equal?*/ 
					begin 
						if(xe == ye)
							state <= addm;
						else 
							if(xe > ye)
							begin	
								ye <= ye + 1;            //up flow
								//y[22:0] <= y[22:0] >> 1;
								ym <= {1'b0, ym[24:1]};
								if(ym == 0)
								begin
									zm <= xm;
									ze <= xe;
									state <= over;
								end
								else
									state <= exequal; 	
							end
							else
							begin
								xe <= xe + 1;            //up flow
								xm	<= {1'b0, xm[24:1]};   // xm >> 1
								if(xm == 0)
								begin
									zm <= ym;
									ze <= ye;
									state <= over;
								end
								else
									state <= exequal;
					      end
					end
					addm:
					begin 
						//{mc,z[31],ms,z[22:0]} <= {x[31],1'b1,x[22:0]} + {y[31],1'b1,y[22:0]}; /*add with carry*/\
						{mc, zm} <= xm + ym;
						ze <= xe;
						if( zm == 25'b0 ) 
						begin
							state <= over;
						end
						else
						begin
							state <= infifl;
						end
					end
					infifl:
					begin 
						if(mc)
						begin
							//{mc,z[31],ms,z[22:0]} <= {mc,z[31],ms,z[22:0]} >> 1;
							zm <= {mc, zm[24:1]};
							ze <= ze + 1;
							if(ze == 8'b1111_1111) /*upward overflow*/
								state <= over;
							else 
								state <= zerofl;
						end
						else
							state <= zerofl;
					end
					zerofl:
					begin    //1.M standarlize
						if(zm[24] == 1'b1)      
						begin
							//{mc,z[31],ms,z[22:0]} <= {mc,z[31],ms,z[22:0]} << 1;
							zm <= {zm[24:1], 1'b0};      // << 1
							ze <= ze - 1;			
							state <= zerofl;
						end
						else if(zm[24:23] == 2'b0 )
						begin
							zm <= {1'b0, zm[23:0]};      // >> 1
							ze <= ze + 1;
							if(ze == 8'b1111_1111)
								state <= over;
							else
								state <= zerofl;
						end
						else
							//z[0] <= 1;
							state <= over;
					end
					over:
					begin 
					end
					idle:
					begin
					end
					default:
					begin
					end
				endcase
			end//task
endmodule