topf.vhd

来自「四位二进制计数器与半加器」· VHDL 代码 · 共 28 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY TOPF IS
 PORT(
       CLKQ:IN STD_LOGIC;
       OUTQ: OUT STD_LOGIC_VECTOR(6 DOWNTO 0)
     );
END TOPF;
ARCHITECTURE FD1 OF TOPF IS
 COMPONENT CNT4
 PORT(
       CLK:IN STD_LOGIC;
        Q: OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
      );
 END COMPONENT;
 COMPONENT DECL7S
 PORT(
      A: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
      LED7S: OUT STD_LOGIC_VECTOR(6 DOWNTO 0)
      );
 END COMPONENT;
 SIGNAL AA: STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
  U1: CNT4 PORT MAP(CLK=>CLKQ,Q=>AA);
  U2: DECL7S PORT MAP(A=>AA,LED7S=>OUTQ);
END ARCHITECTURE FD1;