f_adder.vhd

来自「四位二进制计数器与半加器」· VHDL 代码 · 共 47 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY OR22 IS
    PORT(A,B : IN STD_LOGIC;
           C : OUT STD_LOGIC);
END OR22;
ARCHITECTURE FU1 OF OR22 IS
BEGIN
   C<=A OR B;
END FU1;

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY H_ADDER IS
    PORT(A,B: IN STD_LOGIC;
         CO,SO : OUT STD_LOGIC);
END H_ADDER;
ARCHITECTURE FH1 OF H_ADDER IS
BEGIN
   SO<=(A OR B)AND(A NAND B);
   CO<=NOT(A NAND B);
END FH1;


LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY F_ADDER IS
    PORT(AIN,BIN,CIN : IN STD_LOGIC;
         COUT,SUM : OUT STD_LOGIC);
END F_ADDER;
ARCHITECTURE FD1 OF F_ADDER IS
     COMPONENT H_ADDER
       PORT(A,B: IN STD_LOGIC;
            CO,SO: OUT STD_LOGIC);
     END COMPONENT;
     COMPONENT OR22
       PORT(A,B: IN STD_LOGIC;
              C: OUT STD_LOGIC);
     END COMPONENT;
          SIGNAL D,E,F : STD_LOGIC;
   BEGIN
 U1:H_ADDER PORT MAP( A=>AIN,B=>BIN,CO=>D,SO=>E );
 U2:H_ADDER PORT MAP( A=>E,B=>CIN,CO=>F,SO=>SUM );
 U3:OR22 PORT MAP( A=>D,B=>F,C=>COUT );
END FD1;