cnt4.vhd

来自「四位二进制计数器与半加器」· VHDL 代码 · 共 20 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY CNT4 IS
  PORT(
        CLK:IN STD_LOGIC;
         Q :OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
       );
END CNT4;
ARCHITECTURE ONE OF CNT4 IS
  SIGNAL Q1: STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
PROCESS(CLK)
BEGIN
  IF CLK'EVENT AND CLK='1' THEN Q1<=Q1+1;
  END IF;
  Q<=Q1;
END PROCESS;
END ONE;
--四位二进制计数器