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V 的代码
program.v
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used *
* solely for design, simulation,
program.v
////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2004 Xilinx, Inc.
// All Rights Reserved
//////////////////////////////////////////////////////////
v.c
main (int *p)
{
int a;
a = 0;
p[1] = a;
a = 0;
p[2] = a;
a = 123456;
p[3] = a;
}
v.java
/*
* V.java
* Copyright (C) 2003
*
* $Id: V.java,v 1.5 2005/07/01 14:20:50 hzi Exp $
*/
/*
Copyright (C) 1997-2001 Id Software, Inc.
This program is free software; you can redistribute it and
prom.v
/* Verilog netlist generated by SCUBA ispLever_v50_Production_Build (40) */
/* C:\ispTOOLS5_0\ispfpga\bin\nt\scuba.exe -w -lang verilog -synth synplify -bus_exp 7 -bb -arch ep5g00 -type bram -wp 00 -
xp.v
// --------------------------------------------------------------------
// >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE
prom.v
/* Verilog netlist generated by SCUBA ispLever_v50_Production_Build (40) */
/* C:\ispTOOLS5_0\ispfpga\bin\nt\scuba.exe -w -lang verilog -synth synplify -bus_exp 7 -bb -arch ep5g00 -type bram -wp 00 -
inv.v
`resetall
`timescale 1 ns / 1 ps
`celldefine
module INV (A, Z);
input A;
output Z;
not (Z, A);
endmodule
`endcelldefine
and2.v
`resetall
`timescale 1 ns / 1 ps
`celldefine
module AND2 (A, B, Z);
input A, B ;
output Z;
and (Z, A, B);
endmodule
`endcelldefine
vhi.v
`resetall
`timescale 1 ns / 1 ps
`celldefine
module VHI ( Z );
output Z ;
supply1 VSS;
buf (Z , VSS);
endmodule
`endcelldefine