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E 的代码
e.udo
-- ProjNav VHDL simulation template: e.udo
-- You may edit this file after the line that starts with
-- '-- START' to customize your simulation
-- START user-defined simulation commands
e.vhw
-- F:\VHDL\SHUZIZHONG\SHUZIZHONG
-- VHDL Test Bench created by
-- HDL Bencher 6.1i
-- Sun Dec 07 12:44:06 2008
--
-- Notes:
-- 1) This testbench has been automatically generated from
-- your
e.ant
-- F:\VHDL\SHUZIZHONG\SHUZIZHONG
-- VHDL Annotation T<mark>e</mark>st B<mark>e</mark>nch cr<mark>e</mark>at<mark>e</mark>d by
-- HDL B<mark>e</mark>nch<mark>e</mark>r 6.1i
-- Sun D<mark>e</mark>c 07 12:44:06 2008
LIBRARY I<mark>E</mark><mark>E</mark><mark>E</mark>;
US<mark>E</mark> I<mark>E</mark><mark>E</mark><mark>E</mark>.STD_LOGIC_1164.ALL;
US<mark>E</mark> I<mark>E</mark><mark>E</mark><mark> ...
e.fdo
## NOTE: Do not edit this file.
## Autogenerated by ProjNav (creatfdo.tcl) on Sun Dec 07 12:44:07 中国标准时间 2008
##
vlib work
vcom -93 -explicit yima.vhdl
vcom -93 -explicit e.vhw
vsim -t 1ps
setup.ini
E:\转换软件测试版\转换软件\三菱PLC梯形图转HEX软件试用版V1.1\DATA\设置文件.SETUP
ocdiv0.dat
e+jf=-0.3687783 +j 0.4174208
ocmul0.dat
e+jf=-26.0800000 +j 29.5200000