代码搜索结果

E:/EPM240程序/流水灯LSLED/db/liushuideng.sim.vwf 0 33500 20 1000 0 E:/EPM240程序/流水灯LSLED/liushuideng.vwf 0 43850 20 1000 0

E:/EPM240程序/VGA2/db/VGA.sim.vwf 0 39898 726 33800 0 E:/EPM240程序/VGA2/VGA.vwf 0 1000000 20 1000 0

@E"VRMNFMl;C"RHyVDjCR "VRON:\OD0C\LDHCUsF3#j\$DMbH\V$#b$MD$HV_NUU4H\DLs\bFHN#Ok\V#MHF3;P"RHyVD4CR "VRVN:\OD0C_[bs\bl$s#[\HDlbCC_LC#b\l0Nso\CMb_DD.\6lb_DD.36lPR";yDVHC R.VVR":O\N0_CDb\s[ls$b[H\#lCbD

@E @ # # # # Created by Synplify Verilog HDL Compiler version 3.7.5, Build 159R from Synplicity, Inc. # Copyright 1994-2007 Synplicity, Inc. , All rights reserved. # Synthesis Netlist written

@E"VRMNFMl;C"RHyVDjCR "VRON:\OD0C\LDHCUsF3#j\$DMbH\V$#b$MD$HV_NUU4H\DLs\bFHN#Ok\V#MHF3;P"RHyVD4CR "VRVN:\OD0C_[bs\bl$s#[\HDlbCC_LCEb\8lD\kO#H_l#Hb_DCLbCC3;P"RHyVD.CR qehv' RVHk#FqM3X34BblsH'y;RRCPH

@E @ # # # # Created by Synplify Verilog HDL Compiler version 3.7.5, Build 159R from Synplicity, Inc. # Copyright 1994-2007 Synplicity, Inc. , All rights reserved. # Synthesis Netlist written

E:\fpgaproject\frequence\freque.ngc 1241524253 OK

E:\fpgaproject\ledtest\sp306_led_top.ngc 1241503375 OK

E:\linpingping\ATCA_converge_board\LVDS_Serdes_list_FPGA1\lvds_bist_top_cs.ngc 1231685755 OK

E:/TMP/fpga_div/db/test_div.sim.vwf 0 894308 615 1000000 0 E:/TMP/fpga_div/test_div.vwf 0 1000000 651 1000000 0