代码搜索结果

E:/examples/Examples-10-2/Verilog/db/Diff_io_top.quartus_db Diff_io_top JWU V1

<mark>E</mark>:/l<mark>e</mark>ssons/电路与系统/实验设计/实验/stat<mark>e</mark>/s<mark>e</mark>ri<mark>e</mark>s_d<mark>e</mark>t<mark>e</mark>ction.vwf 0 3462400 541 3462400 0 <mark>E</mark>:/l<mark>e</mark>ssons/电路与系统/实验设计/实验/s<mark>e</mark>ri<mark>e</mark>s_d<mark>e</mark>t<mark>e</mark>ction/db/s<mark>e</mark>ri<mark>e</mark>s_d<mark>e</mark>t<mark>e</mark>ction.sim.vwf 0 2500000 4 ...

E:\Program Files\xp\Xilinx92i\mydesign\vgavga\vgavga.ngc 1212255844 OK

@E"VRMNFMl;C"RHyVDjCR "VROb:\ssFoNVlRH#DC\M#$bODHH\0$#b$MD$HV_\(dD\HLP\E8#308P"E8;VRyHRDC4R V"\8:gD.c$g[\.oc\CsMCNs0F_M#H38PE"y;RVCHDRV. R:"O\FbsolsNRDVHC##\$DMbH0OH$$\#MHbDV($_dH\DLE\P80\#8n44cE3P

e:\program\fpga_program\for_fpga\can\ise\canbus\can_top.ngc 1105409657 OK

@E"VRMNFMl;C"RHyVDjCR "VRO#:\$DMbH0OH$$\#MHbDV($_jH\DLE\P80\#8E3P8R";yDVHC R4VER":N\OMb\ODs8\C4P_\MOF0DsF38PE"y;RVCHDRV. R:"O\M#$bODHH\0$#b$MD$HV_\(jD\HLP\E8#40843ncP"E8;VRyHRDCdR V"\O:#b$MDHHO0#$

@E @ # # # # Created by Synplify Verilog HDL Compiler version 3.7.5, Build 159R from Synplicity, Inc. # Copyright 1994-2007 Synplicity, Inc. , All rights reserved. # Synthesis Netlist written

@E"VRMNFMl;C"RHyVDjCR "VROD:\HsLCF$\#MHbDV#$\$DMbH_V$U4UN\LDH\FbsNO#H\FbsNO#Hd"3P;VRyHRDC4R V"\E:VNbo_#0C0b\VoVN_H_VFj.4._\j.#slN0MoC\VVHFb_Vo.N4UUjG\VVHFb_Vo.N4UUjG3;P"RHyVD.CR "VREV:\b_oN00C#\oVb

E:\合作资料\SHARE-2440\开发文档\SHARE-2440\SHARE_2440_CPLD\SHARE_2440_CPLD\SHARE_2440.ngc 1168614820 OK