e-try.tan.summary

频率计编程 看看吧第一次先贴希望对大家有用

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 0.796 ns
From           : KEY7279
To             : FPGA_7279:inst|key_7279[0]
From Clock     : --
To Clock       : SYS_CLK
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 16.159 ns
From           : FPGA_7279:inst|CS7279
To             : CS7279
From Clock     : SYS_CLK
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 6.985 ns
From           : SYS_RST_N
To             : FPGA_7279:inst|seg_cnt[0]
From Clock     : --
To Clock       : SYS_CLK
Failed Paths   : 0

Type           : Clock Setup: 'SYS_CLK'
Slack          : N/A
Required Time  : None
Actual Time    : 114.67 MHz ( period = 8.721 ns )
From           : div:inst7|fre_N[8]
To             : div:inst7|clk_tmp
From Clock     : SYS_CLK
To Clock       : SYS_CLK
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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