1-Wire总线主机
Abstract: Communication with 1-Wire slave devices requires a 1-Wire master. There are numerous ways to build a 1-Wire master (see reference design 4...
Abstract: Communication with 1-Wire slave devices requires a 1-Wire master. There are numerous ways to build a 1-Wire master (see reference design 4...
Debussy是NOVAS Software, Inc(思源科技)發展的HDL Debug & Analysis tool,這套軟體主要不是用來跑模擬或看波形,它最強大的功能是:能夠在HDL source code、schematic diagram、waveform、state bubble di...
IDCT-M is a medium speed 1D IDCT core -- it can accept a continous stream of 12-bit input words at a rate of -- 1 bit/ck cycle, operating at 50MHz s...
Turbo Decoder Release 0.3 * Double binary, DVB-RCS code * Soft Output Viterbi Algorithm * MyHDL cycle/bit accurate model * Synthesizable VHDL mode...
Hard-decision decoding scheme Codeword length (n) : 31 symbols. Message length (k) : 19 symbols. Error correction capability (t) : 6 symbols O...