1-Wire总线主机
Abstract: Communication with 1-Wire slave devices requires a 1-Wire master. There are numerous way...
synthesizable技术资料
📦 资源总数：19
💻 源代码：640
📚 synthesizable全部资料 (19个)
Debussy是NOVAS Software, Inc(思源科技)發展的HDL Debug & Analysis tool
Debussy是NOVAS Software, Inc(思源科技)發展的HDL Debug & Analysis tool，這套軟體主要不是用來跑模擬或看波形，它最強大的功能是：能夠在HDL sour...
IDCT-M is a medium speed 1D IDCT core -- it can accept a continous stream of 12-bit input words at
IDCT-M is a medium speed 1D IDCT core -- it can accept a continous stream of 12-bit input words at ...
Turbo Decoder Release 0.3 * Double binary, DVB-RCS code * Soft Output Viterbi Algorithm * MyHDL c
Turbo Decoder Release 0.3 * Double binary, DVB-RCS code * Soft Output Viterbi Algorithm * MyHDL c...
Hard-decision decoding scheme Codeword length (n) : 31 symbols. Message length (k) : 19 symbols.
Hard-decision decoding scheme Codeword length (n) : 31 symbols. Message length (k) : 19 symbols....
一个简单的ＳＰＩ ＩＰ核
一个简单的ＳＰＩ ＩＰ核，SPI Core Specifications 可以从说明文档中找到！ The simple Serial Peripheral Interface core is an ...
This lab exercise will introduce you to the AccelWare IP generators. AccelWare is a library of over
This lab exercise will introduce you to the AccelWare IP generators. AccelWare is a library of over ...
可综合的Verilog语法（剑桥大学
可综合的Verilog语法（剑桥大学，影印） Synthesizable Verilogsyntax and semantics...
DDR SDRAM控制器的VHDL源代码
DDR SDRAM控制器的VHDL源代码，含详细设计文档。 The DDR, DCM, and SelectI/O™ features in the Virtex™ -II ar...