it is a verilog code written for MAX1886 ADC interin modelsim simulator and it will synthesize in xinlix ise 8.2i.i have tested it om my kit.
标签： synthesize simulator modelsim interin
上传时间： 2017-03-22
上传用户：洛木卓
it is a verilog code written for digital watch in modelsim simulator and it will synthesize in xinlix ise 8.2i.i have tested it om my kit.[i mae my own kit for spartan2 device]
标签： synthesize simulator modelsim digital
上传时间： 2014-01-10
上传用户：kernaling
it is a verilog code written for FIFO in modelsim simulator and it will synthesize in xinlix ise 8.2i.i have tested it om my kit.[i mae my own kit for spartan2 device].you can use this code in any DSP project in which data entry is required.
标签： synthesize simulator modelsim verilog
上传时间： 2014-06-26
上传用户：zhuyibin
it is a verilog code written for traffic light controller will synthesize in xinlix ise 8.2i.i have tested it om my kit.[i mae my own kit for spartan2 device].it is a state machine based code.
标签： controller synthesize verilog traffic
上传时间： 2017-03-22
上传用户：xymbian
it is a verilog code written for MELAY state machine based UART and it wll synthesize in xinlix ise 8.2i.i have tested it om my kit.[i mae my own kit for spartan2 device]
标签： synthesize verilog machine written
上传时间： 2013-12-11
上传用户：yepeng139
An timer application for AVR mega family processors using unmodified freertos
标签： application processors unmodified freertos
上传时间： 2017-03-24
上传用户：ghostparker
Code signer for iPhone
上传时间： 2017-04-01
上传用户：zgu489
code keil for PC16552D
上传时间： 2014-01-14
上传用户：sunjet
This code is for transmission and reception on 8880,lcd and 24cxx chip using 8051.
标签： transmission and reception using
上传时间： 2013-11-28
上传用户：zhanditian
Freescile MXC91231 source file is containing for hardhat
标签： containing Freescile hardhat source
上传时间： 2014-11-12
上传用户：ghostparker
