单片机系统“PC”失控的软件措施Software Measure of GettingO uto fC ontrolfo r“PC"in S ingleC hipC omputerS ystem谧 加 春 王 晓 基 雷 小 华(江 西 理 工 大 学机 电 工 程 学 院 ，赣 州 34 10 00)摘要单片机系统在实际工业现场中可能遇到各种干扰和自身的随机性故障。现场恶劣的环境有可能使计算机系统发生异常，计算机程序指针“PC”失控就是常见的故障之一，如果发生“PC”失控，将导致CPI工作混乱，酿成严重的事故。研究了“PC”失控的原因，并指出软件抗干扰的几种方法，有效保证单片机系统的正常工作。关键词单片机“PC”失控抗干扰Abstract Inp racticalin dustrialfi elds,th ereis v ariousin terferencea fectingo perationo fsi nglec hipc omputersy stemsa ndt hec omputersy stems。fac吨random faults饰themselves. It is very common that the severe environment makes the computer systems abnormal. The program counter "PC"gettingo utof co ntorlis on eo fth ec ommonfa ults.If th isoc curs,C PUw ouldb eru nningo utof or deran din torducesse riousan cient.T hec ausesof " PC"geting out of control， studied in this paper and some countermeasures of anti-interference师software are given to ensure single chip computer systemworking properly.Keywords Single。饰computer Porgramc ounter"P C" Anti-interfeernc 在设 计 和 开发单片机系统时，一般难以周全地预计单片机系统在实际工业现场中可能遇到的各种干扰和自身的随机性故障。因此，除了采取防止和抑制干扰的各项措施外，还应该借助于软件措施克服某些干扰，系统还应具备迅速自行恢复的能力。本文介绍的应对单片机系统PC失控的软件措施，设计灵活，节省硬件资源，能保证测控系统长期可靠地运行。MC S- 5 1单片机以其优良的性能价格比大量应用于工业现场测试和控制领域。但是，现场恶劣的环境有可能使计算机系统发生异常，计算机程序指针PC失控就是常见的故障之一，一旦发生PC“走飞”，计算机系统就会出现工作混乱，酿成严重的事故。为 了 在 CP 失控时尽量减少由此带来的不利影响，并尽快使系统恢复正常，需要采取一定的软件措施和硬件措施。常见的硬件措施有“看门狗”电路。软件措施设置的前提条件是:①在干扰作用下，微机系统硬件部分不会受到任何损坏，或者损坏部分设置有监测状态可供查询;②程序区不会受到干扰侵害。单片机系统的程序和表格以及重要的参数均设置在ROM区，不会因干扰的侵人而改变;③ RAM区中的重要数据不会被破坏，或者虽然被破坏，但是可以重新建立。
上传时间： 2013-11-02
上传用户：bhqrd30
自动检测80C51 串行通讯中的波特率本文介绍一种在80C51 串行通讯应用中自动检测波特率的方法。按照经验，程序起动后所接收到的第1 个字符用于测量波特率。这种方法可以不用设定难于记忆的开关，还可以免去在有关应用中使用多种不同波特率的烦恼。人们可以设想：一种可靠地实现自动波特检测的方法是可能的，它无须严格限制可被确认的字符。问题是：在各种的条件下，如何可以在大量允许出现的字符中找出波特率的定时间隔。显然，最快捷的方法是检测一个单独位时间（single bit time），以确定接收波特率应该是多少。可是，在RS-232 模式下，许多ASCII 字符并不能测量出一个单独位时间。对于大多数字符来说，只要波特率存在合理波动（这里的波特率是指标准波特率），从起始位到最后一位“可见”位的数据传输周期就会在一定范围内发生变化。此外，许多系统采用8 位数据、无奇偶校验的格式传输ASCII 字符。在这种格式里，普通ASCII 字节不会有MSB 设定
上传时间： 2013-10-15
上传用户：shirleyYim
中文版详情浏览：http://www.elecfans.com/emb/fpga/20130715324029.html Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications. The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation. Some of the UltraScale architecture breakthroughs include: • Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50% • Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability • Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization • 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard • Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets • Greatly enhanced DSP and packet handling The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.
标签： UltraScale Xilinx 架构
上传时间： 2013-11-13
上传用户：瓦力瓦力hong
Abstract: This application note discusses the development and deployment of 3G cellular femtocell base stations. The technicalchallenges for last-mile residential connectivity and adding system capacity in dense urban environments are discussed, with 3Gfemtocell base stations as a cost-effective solution. Maxim's 3GPP TS25.104-compliant transceiver solution is presented along withcomplete radio reference designs such as RD2550. For more information on the RD2550, see reference design 5364, "FemtocellRadio Reference Designs Using the MAX2550–MAX2553 Transceivers."
标签： Base-Station Applications Single-Chip Transceiver
上传时间： 2013-11-07
上传用户：songrui
Express Mode uses an 8-bit wide bus path for fast configuration of Xilinx FPGAs. Thisapplication note provides information on how to perform Express configuration specifically forthe Spartan™-XL family. The Express mode signals and their associated timing are defined.The steps of Express configuration are described in detail, followed by detailed instructions thatshow how to implement the configuration circui
标签： Spartan-XL Express XAPP FPGA
上传时间： 2014-12-28
上传用户：hewenzhi
The PLB BRAM Interface Controller is a module thatattaches to the PLB (Processor Local Bus).
上传时间： 2013-10-27
上传用户：zoudejile
The Xilinx Zynq-7000 Extensible Processing Platform (EPP) redefines the possibilities for embedded systems, giving system and software architects and developers a flexible platform to launch their new solutions and traditional ASIC and ASSP users an alternative that aligns with today’s programmable imperative. The new class of product elegantly combines an industrystandard ARMprocessor-based system with Xilinx 28nm programmable logic—in a single device. The processor boots first, prior to configuration of the programmable logic. This, along with a streamlined workflow, saves time and effort and lets software developers and hardware designers start development simultaneously.
上传时间： 2013-11-01
上传用户：dingdingcandy
This application note covers the design considerations of a system using the performance features of the LogiCORE™ IP Advanced eXtensible Interface (AXI) Interconnect core. The design focuses on high system throughput through the AXI Interconnect core with F MAX and area optimizations in certain portions of the design. The design uses five AXI video direct memory access (VDMA) engines to simultaneously move 10 streams (five transmit video streams and five receive video streams), each in 1920 x 1080p format, 60 Hz refresh rate, and up to 32 data bits per pixel. Each VDMA is driven from a video test pattern generator (TPG) with a video timing controller (VTC) block to set up the necessary video timing signals. Data read by each AXI VDMA is sent to a common on-screen display (OSD) core capable of multiplexing or overlaying multiple video streams to a single output video stream. The output of the OSD core drives the DVI video display interface on the board. Performance monitor blocks are added to capture performance data. All 10 video streams moved by the AXI VDMA blocks are buffered through a shared DDR3 SDRAM memory and are controlled by a MicroBlaze™ processor. The reference system is targeted for the Virtex-6 XC6VLX240TFF1156-1 FPGA on the Xilinx® ML605 Rev D evaluation board
上传时间： 2013-11-14
上传用户：fdmpy
ACNET-600/622是南京来可电子科技有限公司的工业级增强型以太网CAN-bus接口卡/设配器，它内部集成了一路/两路CAN-bus 接口和一路EtherNet 接口以及TCP/IP协议栈，用户利于它可以轻松完成CAN-bus网络和EtherNet 网络的互连互通，进一步拓展CAN-bus 网络的范围。
上传时间： 2013-11-06
上传用户：caozhizhi
简介： ACNET-600/622是南京来可电子科技有限公司的工业级增强型以太网CAN-bus接口卡/设配器，它内部集成了一路/两路CAN-bus 接口和一路EtherNet 接口以及TCP/IP协议栈，用户利于它可以轻松完成CAN-bus网络和EtherNet 网络的互连互通，进一步拓展CAN-bus 网络的范围。 ACNET-600支持一路CAN口，ACNET-622支持两路CAN口。 ACNET-600/622为工业级产品，可以工作在-25℃～+75℃的温度范围内。它具有10M/100M自适应以太网接口，CAN口通信最高波特率为1Mbps，完善的支持TCP Server、TCP Client和UDP等多种工作模式，每个CAN口可支持2个TCP连接或多达2×254个UDP“连接”，通过配置软件用户可以灵活的设定相关配置参数。 特点： • CAN波特率5Kbps～1Mbps，可任意设定； • 发送最高大于3000帧/秒，接收最高大于6000帧/秒； • 隔离电压3000V DC-DC； • UDP方式下每个CAN口支持2个目标IP段，多个用户可同时管理一个CAN设备； • 灵活的CAN报文分帧设置，满足用户各种分包需求。
上传时间： 2013-10-30
上传用户：bruce
