The PLB BRAM Interface Controller is a module thatattaches to the PLB (Processor Local Bus).
上传时间： 2013-10-26
上传用户：zoudejile
The PLB BRAM Interface Controller is a module thatattaches to the PLB (Processor Local Bus).
上传时间： 2013-10-27
上传用户：Breathe0125
基于RAM块的应用
上传时间： 2013-11-02
上传用户：box2000
This application note describes how to build a system that can be used for determining theoptimal phase shift for a Double Data Rate (DDR) memory feedback clock. In this system, theDDR memory is controlled by a controller that attaches to either the OPB or PLB and is used inan embedded microprocessor application. This reference system also uses a DCM that isconfigured so that the phase of its output clock can be changed while the system is running anda GPIO core that controls that phase shift. The GPIO output is controlled by a softwareapplication that can be run on a PowerPC® 405 or Microblaze™ microprocessor.
上传时间： 2013-10-14
上传用户：euroford
This application note describes a reference system which illustrates how to build an embeddedPowerPC® system using the Xilinx 1-Gigabit Ethernet Media Access Controller processor core.This system has the PLB_Gemac configured to use Scatter/Gather Direct Memory Access andthe Serializer/Deserializer (SerDes) interface. This application note describes how to set up thespecific clocking structure required for the SerDes interface and the constraints to be added tothe UCF file. This reference system is complete with a standalone software application to testsome of the main features of this core, including access to registers, DMA capabilities, transmitand receive in loopback mode. This reference system is targeted for the ML300 evaluationboard.
上传时间： 2013-11-01
上传用户：truth12
介绍了SoPC（System on a Programmable Chip）系统的概念和特点，给出了基于PLB总线的异步串行通信（UART）IP核的硬件设计和实现。通过将设计好的UART IP核集成到SoPC系统中加以验证，证明了所设计的UART IP核可以正常工作。该设计方案为其他基于SoPC系统IP核的开发提供了一定的参考。
上传时间： 2013-11-12
上传用户：894448095
基于RAM块的应用
上传时间： 2015-01-01
上传用户：13681659100
This application note describes how to build a system that can be used for determining theoptimal phase shift for a Double Data Rate (DDR) memory feedback clock. In this system, theDDR memory is controlled by a controller that attaches to either the OPB or PLB and is used inan embedded microprocessor application. This reference system also uses a DCM that isconfigured so that the phase of its output clock can be changed while the system is running anda GPIO core that controls that phase shift. The GPIO output is controlled by a softwareapplication that can be run on a PowerPC® 405 or Microblaze™ microprocessor.
上传时间： 2014-11-26
上传用户：erkuizhang
SDRAM 参考设计:主要包括The following figure shows a high-level block diagram for this reference design followed by a brief description of each sub-section. The design consists of: · PowerPC processor · PLB-OPB bridge · BlockRAM Memory Controller · SDRAM Controller · Two GPIO ports · A UART Port · External SDRAM
标签： high-level following reference diagram
上传时间： 2013-12-15
上传用户：Miyuki
Here an embedded System-on-Chip is build, in an Xilinx Spartan-3 FPGA with Microblaze as the processor.A PLB core System is made with the VGA IP core attached to it. The software written for the MicroBlaze processor specifies the object, the color and the movement of the display. The functionality of the module is verified by implementation on Spartan 3.
标签： System-on-Chip Microblaze embedded Spartan
上传时间： 2013-12-19
上传用户：上善若水
