plb_if.v

TFT LCD 控制器的VERILOG 源代码程序,已在某项目上成功应用.

//----------------------------------------------------------------------------
// PLB INTERFACE - Sub Level Module
//-----------------------------------------------------------------------------
//
//     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
//     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR
//     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION
//     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION
//     OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS
//     IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
//     AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
//     FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY
//     WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
//     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
//     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
//     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
//     FOR A PARTICULAR PURPOSE.
//     
//     (c) Copyright 2004 Xilinx, Inc.
//     All rights reserved.
// 
//----------------------------------------------------------------------------
// Filename:     plb_if.v
// 
// Description:    
// 
//
// Design Notes:
//   
//-----------------------------------------------------------------------------
// Structure:   
// 
//-----------------------------------------------------------------------------
// Author:              CJN
// History:
//      CJN, MM 3/02    -- First Release
//      CJN                             -- Second Release
//
//
//-----------------------------------------------------------------------------

///////////////////////////////////////////////////////////////////////////////
// Module Declaration
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ns / 100 ps
module plb_if(
  // PLB GLOBAL SIGNALS
  clk,               // I  100MHz
  rst,               // I 

   // REQUEST QUALIFIERS INPUTS
  PLB_MnAddrAck,     // I
  Mn_request,        // O
  Mn_priority,       // O [0:1]
  Mn_RNW,            // O
  Mn_BE,             // O [0:7]
  Mn_size,           // O [0:3]
  Mn_type,           // O [0:2]
  Mn_MSize,          // O [0:1]          
  Mn_ABus,           // O [0:31]

  // PLB READ DATA BUS              
  PLB_MnRdDAck,      // I
  PLB_MnRdWdAddr,    // I
  PLB_MnRdDBus,      // I [0:63]       
  PLB_MnRdBTerm,     // I
  Mn_rdBurst,        // O

  // PLB_BRAM CONTROL AND DATA
  PLB_BRAM_data,     // O [0:63]
  PLB_BRAM_we,       // O 

  // GET_LINE PULSE
  get_line,          // I

  // BASE ADDRESS
  tft_base_addr,     // I [0:10]
  tft_on_reg         // I
  );

///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////

  // PLB GLOBAL SIGNALS
  input          clk;
  input          rst;

  // REQUEST QUALIFIERS INPUTS
  input          PLB_MnAddrAck;
  output         Mn_request;
  output [0:1]   Mn_priority;
  output         Mn_RNW;
  output [0:7]   Mn_BE;
  output [0:3]   Mn_size;        
  output [0:2]   Mn_type;
  output [0:1]   Mn_MSize;                 
  output [0:31]  Mn_ABus;

  // PLB READ DATA BUS
  input          PLB_MnRdDAck;     
  input [0:3]    PLB_MnRdWdAddr;
  input [0:63]   PLB_MnRdDBus;        
  input          PLB_MnRdBTerm;
  output         Mn_rdBurst;

  // PLB_BRAM CONTROL AND DATA
  output [0:63]  PLB_BRAM_data;
  output         PLB_BRAM_we;

  // GET LINE PULSE
  input          get_line;
  input [0:10]   tft_base_addr;
  input          tft_on_reg;

///////////////////////////////////////////////////////////////////////////////
// Signal Declaration
///////////////////////////////////////////////////////////////////////////////

  reg         Mn_rdBurst;

  reg  [0:4]  trans_cnt;
  reg  [0:4]  trans_cnt_i;
  wire        trans_cnt_ce;
  wire        trans_cnt_tc;

  reg  [0:8]  line_cnt;
  reg  [0:8]  line_cnt_i;
  wire        line_cnt_ce;

  wire        end_xfer;
  wire        end_xfer_p1;

  reg  [0:63] PLB_BRAM_data;
  reg  [0:1]  PLB_BRAM_addr_lsb;
  reg         PLB_BRAM_we;
  reg  [0:10] tft_base_addr_i;

  wire        skip_line;
  reg         skip_line_d1;
  reg  [4:0]  skip_plb_xfer_cnt;
  wire        dummy_rd_ack;
  wire        mn_request_set;
  reg  [0:15] data_xfer_shreg;
  reg         data_xfer_shreg1_d1;

  reg         last_rdack;
  reg  [4:0]  flush_cnt;
  wire        flush_rdack;

  ////////////////////////////////////////////////////////////////////////////
  // Tie off Constants
  ////////////////////////////////////////////////////////////////////////////

  assign Mn_MSize     = 2'b01;             // 64 Bit PLB Xfers 
  assign Mn_priority  = 2'b11;             // Set priority to 3
  assign Mn_size      = 4'b1011;           // Transfer 8-word line 
  assign Mn_type      = 3'b000;            // Memory type transfer
  assign Mn_RNW       = 1'b1;              // Always read
  assign Mn_BE        = 8'b11110000;       // Ignored on Line xfers
  assign Mn_ABus[0:10]  = tft_base_addr_i; // 11-bits
  assign Mn_ABus[11:19] = line_cnt_i;
  assign Mn_ABus[20:24] = trans_cnt_i;
  assign Mn_ABus[25:31] = 7'b0000000;
  
  assign mn_request_set = tft_on_reg & (  (get_line & (trans_cnt == 0))
                                        | (end_xfer & (trans_cnt != 0)));
  FDRSE FDRS_MN_REQUEST_DLY (.Q(Mn_request),.CE(1'b0),.C(clk),.D(1'b0),
                             .R(PLB_MnAddrAck | rst), .S(mn_request_set));

  always @(posedge clk)
  begin
     if (rst)
       skip_plb_xfer_cnt <= 5'b0;
     else if (~tft_on_reg & (  (get_line & (trans_cnt == 0))
                             | (end_xfer & (trans_cnt != 0))))
       skip_plb_xfer_cnt <= 5'd16;
     else if (| skip_plb_xfer_cnt)
       skip_plb_xfer_cnt <= skip_plb_xfer_cnt - 1;
     end
  assign dummy_rd_ack = (| skip_plb_xfer_cnt);

  always @(posedge clk)
    if (mn_request_set) begin
      tft_base_addr_i <= tft_base_addr;
      line_cnt_i      <= line_cnt;
      trans_cnt_i     <= trans_cnt;
    end             

  always @(posedge clk)
  begin
    PLB_BRAM_data     <= PLB_MnRdDBus;
    PLB_BRAM_we       <= PLB_MnRdDAck | dummy_rd_ack | flush_rdack;
  end

  always @(posedge clk)
    if (rst | end_xfer)
      data_xfer_shreg <= (end_xfer & (PLB_MnRdDAck | dummy_rd_ack | flush_rdack))? 16'b0000_0000_0000_0001 : 16'b0000_0000_0000_0000;
    else if (PLB_MnRdDAck | dummy_rd_ack | flush_rdack)
      data_xfer_shreg <= {data_xfer_shreg[1:15], 1'b1};

  assign end_xfer = data_xfer_shreg[0];

  always @(posedge clk)
    data_xfer_shreg1_d1 <= data_xfer_shreg[1];

  assign end_xfer_p1 = data_xfer_shreg[1] & ~data_xfer_shreg1_d1;

///////////////////////////////////////////////////////////////////////////////
// Transaction Counter - Counts 0-79 (d)
///////////////////////////////////////////////////////////////////////////////      

  assign trans_cnt_ce = end_xfer_p1;
  assign trans_cnt_tc = (trans_cnt == 7'd19);

  always @(posedge clk)
    if(rst)
      trans_cnt = 5'b0;
    else if (trans_cnt_ce) begin
      if (trans_cnt_tc)
        trans_cnt = 5'b0;
      else 
        trans_cnt = trans_cnt + 1;
      end

///////////////////////////////////////////////////////////////////////////////
// Line Counter - Counts 0-479 (d)
///////////////////////////////////////////////////////////////////////////////      

  // increment line cnt if getline missed because prev plb xfers not complete
  assign skip_line = get_line & (trans_cnt != 0);
  always @(posedge clk)
    skip_line_d1 <= skip_line & line_cnt_ce;

  assign line_cnt_ce = end_xfer_p1 & trans_cnt_tc;

  always @(posedge clk)
    if (rst)
      line_cnt = 9'b0;
    else if (line_cnt_ce | skip_line | skip_line_d1) begin
      if (line_cnt == 9'd479)
        line_cnt = 9'b0;
      else
        line_cnt = line_cnt + 1;
    end

///////////////////////////////////////////////////////////////////////////////
// Generate burst transfer control signals for PLB
///////////////////////////////////////////////////////////////////////////////      

always @(posedge clk)
    if(rst)
      Mn_rdBurst <= 1'b0;
    else if (PLB_MnAddrAck)
      Mn_rdBurst <= 1'b1;
    else if (PLB_MnRdBTerm)
      Mn_rdBurst <= 1'b0;

// If PLB Burst is terminated early, stuff unfilled data slots

always @(posedge clk)
    if(rst | PLB_MnAddrAck)
      last_rdack <= 1'b0;
    else if (!Mn_rdBurst & PLB_MnRdDAck)
      last_rdack <= 1'b1;

always @(posedge clk)
    if(rst)
      flush_cnt <= 5'b0;
    else if (PLB_MnAddrAck)
      flush_cnt <= 5'd16;
    else if (PLB_MnRdDAck)
      flush_cnt <= flush_cnt - 1;
    else if (last_rdack)
      if (| flush_cnt) flush_cnt <= flush_cnt - 1;

assign flush_rdack = last_rdack & (| flush_cnt);

endmodule