This effort started as an answer to the numerous questions the authors have repeatedly had to answer about electrostatic discharge (ESD) protection and input/output (1/0) designs. In the past no comprehensive book existed suffi- ciently covering these areas, and these topics were rarely taught in engineering schools. Thus first-time I/O and ESD protection designers have had consider- able trouble getting started. This book is in part an answer to such needs.
上传时间： 2020-06-05
上传用户：shancjb
Recent work has shown that convolutional networks can be substantially deeper, more accurate, and efficient to train if they contain shorter connections between layers close to the input and those close to the output. In this paper, we embrace this observation and introduce the Dense Convo- lutional Network (DenseNet), which connects each layer to every other layer in a feed-forward fashion.
标签： Convolutional Connected Networks Densely
上传时间： 2020-06-10
上传用户：shancjb
lm75A温度数字转换器 FPGA读写实验Verilog逻辑源码Quartus工程文件+文档资料,FPGA为CYCLONE4系列中的EP4CE6E22C8. 完整的工程文件，可以做为你的学习设计参考。LM75A 是一个使用了内置带隙温度传感器和模数转换技术的温度数字转换器。它也是一个温度检测器，可提供一个过热检测输出。LM75A 包含许多数据寄存器：配置寄存器用来存储器件的某些配置，如器件的工作模式、OS 工作模式、OS 极性和OS 故障队列等（在功能描述一节中有详细描述）；温度寄存器（Temp），用来存储读取的数字温度；设定点寄存器（Tos & Thyst），用来存储可编程的过热关断和滞后限制，器件通过2 线的串行I2C 总线接口与控制器通信。LM75A 还包含一个开漏输出（OS），当温度超过编程限制的值时该输出有效。LM75A 有3 个可选的逻辑地址管脚，使得同一总线上可同时连接8个器件而不发生地址冲突。LM75A 可配置成不同的工作条件。它可设置成在正常工作模式下周期性地对环境温度进行监控或进入关断模式来将器件功耗降至最低。OS 输出有2 种可选的工作模式：OS 比较器模式和OS 中断模式。OS 输出可选择高电平或低电平有效。故障队列和设定点限制可编程，为了激活OS 输出，故障队列定义了许多连续的故障。温度寄存器通常存放着一个11 位的二进制数的补码，用来实现0.125℃的精度。这个高精度在需要精确地测量温度偏移或超出限制范围的应用中非常有用。正常工作模式下，当器件上电时，OS 工作在比较器模式，温度阈值为80℃，滞后75℃，这时，LM75A就可用作一个具有以上预定义温度设定点的独立的温度控制器。module LM75_SEG_LED ( //input input sys_clk ,input sys_rst_n ,inout sda_port ,//output output wire seg_c1 ,output wire seg_c2 ,output wire seg_c3 ,output wire seg_c4 ,output reg seg_a ,output reg seg_b ,output reg seg_c ,output reg seg_e ,output reg seg_d ,output reg seg_f ,output reg seg_g ,output reg seg_h , output reg clk_sclk );//parameter define parameter WIDTH = 8;parameter SIZE = 8;//reg define reg [WIDTH-1:0] counter ;reg [9:0] counter_div ;reg clk_50k ;reg clk_200k ;reg sda ;reg enable ;
上传时间： 2021-10-27
上传用户：
FPGA采样AD9238数据并通过VGA波形显示例程 Verilog逻辑源码Quartus工程文件+文档说明,FPGA型号Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。ADC 模块型号为 AN9238，最大采样率 65Mhz，精度为12 位。实验中把 AN9238 的 2 路输入以波形方式在 HDMI 上显示出来，我们可以用更加直观的方式观察波形，是一个数字示波器雏形。module top( input clk, input rst_n, output ad9238_clk_ch0, output ad9238_clk_ch1, input[11:0] ad9238_data_ch0, input[11:0] ad9238_data_ch1, //vga output output vga_out_hs, //vga horizontal synchronization output vga_out_vs, //vga vertical synchronization output[4:0] vga_out_r, //vga red output[5:0] vga_out_g, //vga green output[4:0] vga_out_b //vga blue);wire video_clk;wire video_hs;wire video_vs;wire video_de;wire[7:0] video_r;wire[7:0] video_g;wire[7:0] video_b;wire grid_hs;wire grid_vs;wire grid_de;wire[7:0] grid_r;wire[7:0] grid_g;wire[7:0] grid_b;wire wave0_hs;wire wave0_vs;wire wave0_de;wire[7:0] wave0_r;wire[7:0] wave0_g;wire[7:0] wave0_b;wire wave1_hs;wire wave1_vs;wire wave1_de;wire[7:0] wave1_r;wire[7:0] wave1_g;wire[7:0] wave1_b;wire adc_clk;wire adc0_buf_wr;wire[10:0] adc0_buf_addr;wire[7:0] adc0_bu
上传时间： 2021-10-27
上传用户：qingfengchizhu
FPGA读写SD卡读取BMP图片通过LCD显示例程实验 Verilog逻辑源码Quartus工程文件+文档说明,FPGA型号Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。1 实验简介在前面的实验中我们练习了 SD 卡读写，VGA 视频显示等例程，本实验将 SD 卡里的 BMP 图片读出，写入到外部存储器，再通过 VGA、LCD 等显示。本实验如果通过液晶屏显示，需要有液晶屏模块。2 实验原理在前面的实验中我们在 VGA、LCD 上显示的是彩条，是 FPGA 内部产生的数据，本实验将彩条替换为 SD 内的 BMP 图片数据，但是 SD 卡读取速度远远不能满足显示速度的要求，只能先写入外部高速 RAM，再读出后给视频时序模块显示module top( input clk, input rst_n, input key1, output [5:0] seg_sel, output [7:0] seg_data, output vga_out_hs, //vga horizontal synchronization output vga_out_vs, //vga vertical synchronization output[4:0] vga_out_r, //vga red output[5:0] vga_out_g, //vga green output[4:0] vga_out_b, //vga blue output sd_ncs, //SD card chip select (SPI mode) output sd_dclk, //SD card clock output sd_mosi, //SD card controller data output input sd_miso, //SD card controller data input output sdram_clk, //sdram clock output sdram_cke, //sdram clock enable output sdram_cs_n, //sdram chip select output sdram_we_n, //sdram write enable output sdram_cas_n, //sdram column address strobe output sdram_ras_n, //sdram row address strobe output[1:0] sdram_dqm, //sdram data enable output[1:0] sdram_ba, //sdram bank address output[12:0] sdram_addr, //sdram address inout[15:0] sdram_dq //sdram data);parameter MEM_DATA_BITS = 16 ; //external memory user interface data widthparameter ADDR_BITS = 24
标签： fpga
上传时间： 2021-10-27
上传用户：
Research on microwave power amplififiers has gained a growing importance demanded by the many continuously developing applications which require such subsystem performance. A broad set of commercial and strategic systems in fact have their overall performance boosted by the power amplififier, the latter becoming an enabling component wherever its effificiency and output power actually allows functionalities and operating modes previously not possible. This is the case for the many wireless systems and battery-operated systems that form the substrate of everyday life, but also of high-performance satellite and dual-use systems.
上传时间： 2021-10-30
上传用户：得之我幸78
基于TMS320F2812 光伏并网发电模拟装置PROTEL设计原理图+PCB+软件源码+WORD论文文档,硬件采用2层板设计，PROTEL99SE 设计的工程文件，包括完整的原理图和PCB文件，可以做为你的学习设计参考。 摘要：本文实现了一个基于TMS320F2812 DSP芯片的光伏并网发电模拟装置，采用直流稳压源和滑动变阻器来模拟光伏电池。通过TMS320F2812 DSP芯片ADC模块实时采样模拟电网电压的正弦参考信号、光伏电池输出电压、负载电压电流反馈信号等。经过数据处理后，用PWM模块产生实时的SPWM 波，控制MOSFET逆变全桥输出正弦波。本文用PI控制算法实现了输出信号对给定模拟电网电压的正弦参考信号的频率和相位跟踪，用恒定电压法实现了光伏电池最大功率点跟踪（MPPT），从而达到模拟并网的效果。另外本装置还实现了光伏电池输出欠压、负载过流保护功能以及光伏电池输出欠压、过流保护自恢复功能、声光报警功能、孤岛效应的检测、保护与自恢复功能。系统测试结果表明本设计完全满定设计要求。关键词：光伏并网，MPPT，DSP Photovoltaic Grid-connected generation simulator Zhangyuxin，Tantiancheng，Xiewuyang(College of Electrical Engineering, Chongqing University)Abstract: This paper presents a photovoltaic grid-connected generation simulator which is based on TMS320F2812 DSP, with a DC voltage source and a variable resistor to simulate the characteristic of photovoltaic cells. We use the internal AD converter to real-time sampling the referenced grid voltage signal, outputting voltage of photovoltaic, feedback outputting voltage and current signal. The PWM module generates SVPWM according to the calculation of the real-time sampling data, to control the full MOSFET inverter bridge output sine wave. We realized that the output voltage of the simulator can track the frequency and phase of the referenced grid voltage with PI regulation, and the maximum photovoltaic power tracking with constant voltage regulation, thereby achieved the purpose of grid-connected simulation. Additionally, this device has the over-voltage and over-current protection, audible and visual alarm, islanding detecting and protection, and it can recover automatically. The testing shows that our design is feasible.Keywords: Photovoltaic Grid-connected，MPPT，DSP 目录引言 11. 方案论证 11.1. 总体介绍 11.2. 光伏电池模拟装置 11.3. DC-AC逆变桥 11.4. MOSFET驱动电路方案 21.5. 逆变电路的变频控制方案 22. 理论分析与计算 22.1. SPWM产生 22.1.1. 规则采样法 22.1.2. SPWM 脉冲的计算公式 32.1.3. SPWM 脉冲计算公式中的参数计算 32.1.4. TMS320F2812 DSP控制器的事件管理单元 42.1.5. 软件设计方法 62.2. MPPT的控制方法与参数计算 72.3. 同频、同相的控制方法和参数计算 8
标签： tms320f2812 光伏 并网发电 模拟 protel pcb
上传时间： 2021-11-02
上传用户：
IIC接口E2PROM(AT24C64) 读写VERILOG 驱动源码+仿真激励文件:module i2c_dri #( parameter SLAVE_ADDR = 7'b1010000 , //EEPROM从机地址 parameter CLK_FREQ = 26'd50_000_000, //模块输入的时钟频率 parameter I2C_FREQ = 18'd250_000 //IIC_SCL的时钟频率 ) ( input clk , input rst_n , //i2c interface input i2c_exec , //I2C触发执行信号 input bit_ctrl , //字地址位控制(16b/8b) input i2c_rh_wl , //I2C读写控制信号 input [15:0] i2c_addr , //I2C器件内地址 input [ 7:0] i2c_data_w , //I2C要写的数据 output reg [ 7:0] i2c_data_r , //I2C读出的数据 output reg i2c_done , //I2C一次操作完成 output reg i2c_ack , //I2C应答标志 0:应答 1:未应答 output reg scl , //I2C的SCL时钟信号 inout sda , //I2C的SDA信号 //user interface output reg dri_clk //驱动I2C操作的驱动时钟 );//localparam definelocalparam st_idle = 8'b0000_0001; //空闲状态localparam st_sladdr = 8'b0000_0010; //发送器件地址(slave address)localparam st_addr16 = 8'b0000_0100; //发送16位字地址localparam st_addr8 = 8'b0000_1000; //发送8位字地址localparam st_data_wr = 8'b0001_0000; //写数据(8 bit)localparam st_addr_rd = 8'b0010_0000; //发送器件地址读localparam st_data_rd = 8'b0100_0000; //读数据(8 bit)localparam st_stop = 8'b1000_0000; //结束I2C操作//reg definereg sda_dir ; //I2C数据(SDA)方向控制reg sda_out ; //SDA输出信号reg st_done ; //状态结束reg wr_flag ; //写标志reg [ 6:0] cnt ; //计数reg [ 7:0] cur_state ; //状态机当前状态reg [ 7:0] next_state; //状态机下一状态reg [15:0] addr_t ; //地址reg [ 7:0] data_r ; //读取的数据reg [ 7:0] data_wr_t ; //I2C需写的数据的临时寄存reg [ 9:0] clk_cnt ; //分频时
标签： iic 接口 e2prom at24c64 verilog 驱动 仿真
上传时间： 2021-11-05
上传用户：
ABSTRACTThe flyback power stage is a popular choice for single and multiple output dc-to-dc converters at powerlevels of 150 Watts or less. Without the output inductor required in buck derived topologies, such as theforward or push-pull converter, the component count and cost are reduced. This application note will reviewthe design procedure for the power stage and control electronics of a flyback converter. In these isolatedconverters, the error signal from the secondary still needs to cross the isolation boundary to achieveregulation. By using the UC3965 Precision Reference with Low Offset Error Amplifier on the secondaryside to drive an optocoupler and the UCC3809 Economy Primary Side Controller on the primary side, asimple and low cost 50 Watt isolated power supply is realized.
标签： 隔离
上传时间： 2021-11-24
上传用户：kingwide
General Design Specification:1. AC Input Range 180-264Vac, Isolated ac-dc offline, 12LEDS,output 700mA2. Intelligent wall dimmer detections(Leading-edge dimmer , Trailing-edgedimmer , No-dimmer)3. Multiple dimming control scheme4. Wide dimming range from 1% up to 100%5. No visible flicker6. Resonant control to achieve high efficiency7. High Power Factor, 0.9 without dimmer8. Temperature degrade control to adjust the LED9. Primary-only Sensing eliminates opto-isolator feedback and simplifies design
标签： iw3617
上传时间： 2021-12-03
上传用户：canderile
