This is is a bridge IP core to interface the Tensilica PIF bus protocol with the OpenCores WishBone.
This is is a bridge IP core to interface the Tensilica PIF bus protocol with the OpenCores WishBone....
This is is a bridge IP core to interface the Tensilica PIF bus protocol with the OpenCores WishBone....
VHDL CODE FOR MULTY CYCLE...
Abstract: This application note describes how sampling clock jitter (time interval error or "...
ANALOG INPUT BANDWIDTH is a measure of the frequencyat which the reconstructed output fundamental dr...
Abstract: Investment in smart meters and smart grid end equipment continues to grow worldwide as c...
介绍了用单片机C 语言实现无功补偿中电容组循环投切的基本原理和算法,并举例说明。关键词:循环投切;C51;无功补偿中图分类号: TM76 文献标识码: BAbstract: This paper in...
All inputs of the C16x family have Schmitt-Trigger input characteristics. These Schmitt-Triggers are...
All inputs of the C16x family have Schmitt-Trigger input characteristics. These Schmitt-Triggers are...
CodeWarrior Development Tool Suites are comprehensive integrated developmentenvironments (IDE) tha...
The LPC4350/30/20/10 are ARM Cortex-M4 based microcontrollers for embeddedapplications. The ARM Cort...