The PCA9516 is a BiCMOS integrated circuit intended forapplication in I2C and SMBus systems.While retaining all the operating modes and features of the I2Csystem, it permits extension of the I2C-bus by buffering both the data(SDA) and the clock (SCL) lines, thus enabling five buses of 400 pF.The I2C-bus capacitance limit of 400 pF restricts the number ofdevices and bus length. Using the PCA9516 enables the systemdesigner to divide the bus into five segments off of a hub where anysegment to segment transition sees only one repeater delay.
上传时间： 2013-11-21
上传用户：q123321
The PCA9540B is a 1-of-2 bidirectional translating multiplexer, controlled via the I2C-bus.The SCL/SDA upstream pair fans out to two SCx/SDx downstream pairs, or channels.Only one SCx/SDx channel is selected at a time, determined by the contents of theprogrammable control register.
上传时间： 2014-12-28
上传用户：nshark
The PCA9541 is a 2-to-1 I2C-bus master selector designed for high reliability dual masterI2C-bus applications where system operation is required, even when one master fails orthe controller card is removed for maintenance. The two masters (for example, primaryand back-up) are located on separate I2C-buses that connect to the same downstreamI2C-bus slave devices. I2C-bus commands are sent by either I2C-bus master and are usedto select one master at a time. Either master at any time can gain control of the slavedevices if the other master is disabled or removed from the system. The failed master isisolated from the system and will not affect communication between the on-line masterand the slave devices on the downstream I2C-bus.
上传时间： 2013-10-09
上传用户：3294322651
The PCA9544A provides 4 interrupt inputs, one for each channeland one open drain interrupt output. When an interrupt is generated byany device, it will be detected by the PCA9544A and the interruptoutput will be driven LOW. The channel need not be active fordetection of the interrupt. A bit is also set in the control byte.Bits 4 – 7 of the control byte correspond to channels 0 – 3 of thePCA9544A, respectively. Therefore, if an interrupt is generated byany device connected to channel 2, the state of the interrupt inputs isloaded into the control register when a read is accomplished.Likewise, an interrupt on any device connected to channel 0 wouldcause bit 4 of the control register to be set on the read. The mastercan then address the PCA9544A and read the contents of thecontrol byte to determine which channel contains the devicegenerating the interrupt. The master can then reconfigure thePCA9544A to select this channel, and locate the device generatingthe interrupt and clear it. The interrupt clears when the deviceoriginating the interrupt clears.
标签： 4channel multiple 9544A 9544
上传时间： 2014-12-28
上传用户：潜水的三贡
The PCA9542A is a 1-of-2 bidirectional translating multiplexer, controlled via the I2C-bus.The SCL/SDA upstream pair fans out to two SCx/SDx downstream pairs, or channels.Only one SCx/SDx channel is selected at a time, determined by the contents of theprogrammable control register. Two interrupt inputs, INT0 and INT1, one for each of theSCx/SDx downstream pairs, are provided. One interrupt output, INT, which acts as anAND of the two interrupt inputs, is provided.
上传时间： 2013-12-07
上传用户：europa_lin
The PCA9547 is an octal bidirectional translating multiplexer controlled by the I2C-bus.The SCL/SDA upstream pair fans out to eight downstream pairs, or channels. Only oneSCx/SDx channel can be selected at a time, determined by the contents of theprogrammable control register. The device powers up with Channel 0 connected, allowingimmediate communication between the master and downstream devices on that channel.
上传时间： 2014-12-28
上传用户：270189020
The PCA9548A is an octal bidirectional translating switch controlled via the I2C-bus. TheSCL/SDA upstream pair fans out to eight downstream pairs, or channels. Any individualSCx/SDx channel or combination of channels can be selected, determined by thecontents of the programmable control register.An active LOW reset input allows the PCA9548A to recover from a situation where one ofthe downstream I2C-buses is stuck in a LOW state. Pulling the RESET pin LOW resets theI2C-bus state machine and causes all the channels to be deselected as does the internalPower-on reset function.
上传时间： 2013-10-13
上传用户：bakdesec
The Philips family of Multiplexers and Switches consists of bi-directional translating switches controlled via the I2C or SMBus to fan out an upstream SCL/SDA pair to 2, 4 or 8 downstream channels of SCx/SDx pairs. The Multiplexers allow only one downstream channel to be selected at a time, while the Switches allow any individual downstream channel or combination of downstream channels to be selected, depending on the content of the programmable control register. Once one or several channels have been selected, the device acts as a wire, allowing the master on the upstream channel to send commands to devices on all the active downstream channels, and devices on the active downstream channels to communicate with each other and the master. External pull-up resistors are used to pull each individual channel up to the desired voltage level. Combined interrupt output and hardware reset input are device options that are featured.
上传时间： 2013-10-11
上传用户：dianxin61
本文依据集成电路设计方法学，探讨了一种基于标准Intel 8086 微处理器的单芯片计算机平台的架构。研究了其与SDRAM，8255 并行接口等外围IP 的集成，并在对AMBA协议和8086 CPU分析的基础上，采用遵从AMBA传输协议的系统总线代替传统的8086 CPU三总线结构，搭建了基于8086 IP 软核的单芯片计算机系统，并实现了FPGA 功能演示。关键词：微处理器； SoC；单芯片计算机；AMBA 协议 Design of 8086 CPU Based Computer-on-a-chip System（School of Electrical Engineering and Automation, Heifei University of Technology, Hefei, 230009,China）Abstract: According to the IC design methodology, this paper discusses the design of one kind of Computer-on-a-chip system architecture, which is based on the standard Intel8086 microprocessor,investigates how to integrate the 8086 CPU and peripheral IP such as, SDRAM controller, 8255 PPI etc. Based on the analysis of the standard Intel8086 microprocessor and AMBA Specification,the Computer-on-a-chip system based on 8086 CPU which uses AMBA bus instead of traditional three-bus structure of 8086 CPU is constructed, and the FPGA hardware emulation is fulfilled.Key words: Microprocessor; SoC; Computer-on-a-chip; AMBA Specification
上传时间： 2013-12-27
上传用户：kernor
用单片机AT89C51改造普通双桶洗衣机：AT89C2051作为AT89C51的简化版虽然去掉了P0、P2等端口，使I/O口减少了，但是却增加了一个电压比较器，因此其功能在某些方面反而有所增强，如能用来处理模拟量、进行简单的模数转换等。本文利用这一功能设计了一个数字电容表，可测量容量小于2微法的电容器的容量，采用3位半数字显示，最大显示值为1999，读数单位统一采用毫微法（nf），量程分四档，读数分别乘以相应的倍率。电路工作原理 本数字电容表以电容器的充电规律作为测量依据，测试原理见图1。电源电路图。 压E+经电阻R给被测电容CX充电，CX两端原电压随充电时间的增加而上升。当充电时间t等于RC时间常数τ时，CX两端电压约为电源电压的63.2%，即0.632E+。数字电容表就是以该电压作为测试基准电压，测量电容器充电达到该电压的时间，便能知道电容器的容量。例如，设电阻R的阻值为1千欧，CX两端电压上升到0.632E+所需的时间为1毫秒，那么由公式τ=RC可知CX的容量为1微法。 测量电路如图2所示。A为AT89C2051内部构造的电压比较器，AT89C2051 图2 的P1.0和P1.1口除了作I/O口外，还有一个功能是作为电压比较器的输入端，P1.0为同相输入端，P1.1为反相输入端，电压比较器的比较结果存入P3.6口对应的寄存器，P3.6口在AT89C2051外部无引脚。电压比较器的基准电压设定为0.632E+，在CX两端电压从0升到0.632E+的过程中，P3.6口输出为0，当电池电压CX两端电压一旦超过0.632E+时，P3.6口输出变为1。以P3.6口的输出电平为依据，用AT89C2051内部的定时器T0对充电时间进行计数，再将计数结果显示出来即得出测量结果。整机电路见图3。电路由单片机电路、电容充电测量电路和数码显示电路等 图3 部分组成。AT89C2051内部的电压比较器和电阻R2-R7等组成测量电路，其中R2-R5为量程电阻，由波段开关S1选择使用，电压比较器的基准电压由5V电源电压经R6、RP1、R7分压后得到，调节RP1可调整基准电压。当P1.2口在程序的控制下输出高电平时，电容CX即开始充电。量程电阻R2-R5每档以10倍递减，故每档显示读数以10倍递增。由于单片机内部P1.2口的上拉电阻经实测约为200K，其输出电平不能作为充电电压用，故用R5兼作其上拉电阻，由于其它三个充电电阻和R5是串联关系，因此R2、R3、R4应由标准值减去1K，分别为999K、99K、9K。由于999K和1M相对误差较小，所以R2还是取1M。数码管DS1-DS4、电阻R8-R14等组成数码显示电路。本机采用动态扫描显示的方式，用软件对字形码译码。P3.0-P3.5、P3.7口作数码显示七段笔划字形码的输出，P1.3-P1.6口作四个数码管的动态扫描位驱动码输出。这里采用了共阴数码管，由于AT89C2051的P1.3-P1.6口有25mA的下拉电流能力，所以不用三极管就能驱动数码管。R8-R14为P3.0-P3.5、P3.7口的上拉电阻，用以驱动数码管的各字段，当P3的某一端口输出低电平时其对应的字段笔划不点亮，而当其输出高电平时，则对应的上拉电阻即能点亮相应的字段笔划。
上传时间： 2013-12-31
上传用户：ming529
