two counters pick up data from two encoders.
标签： two counters encoders pick
上传时间： 2013-12-16
上传用户：xymbian
The CD4020BC, CD4060BC are 14-stage ripple carrybinary counters, and the CD4040BC is a 12-sta
上传时间： 2013-05-15
上传用户：ajaxmoon
英文描述： Synchronous Up/Down Decade counters(single clock line) 中文描述： 同步向上/向下十年计数器（单时钟线）
上传时间： 2013-06-18
上传用户：haohaoxuexi
S3C8-SERIESMCU 三星的SAM8RC系列8位单片机向用户提供了高效快速的CPU，丰富的外围接口，以及各种大小的可编程ROM。 它的地址/数据总线结构和位可编程I/O口为用户提供了一个灵活的编程环境，能够满足不同用户对存储器和I/O口的不同要求。同时，具有可选工作模式的Timer/counters可支持实时操作。
上传时间： 2014-07-12
上传用户：农药锋6
各种功能的计数器实例（VHDL源代码）:ENTITY counters IS PORT ( d : IN INTEGER RANGE 0 TO 255; clk : IN BIT; clear : IN BIT; ld : IN BIT; enable : IN BIT; up_down : IN BIT; qa : OUT INTEGER RANGE 0 TO 255; qb : OUT INTEGER RANGE 0 TO 255; qc : OUT INTEGER RANGE 0 TO 255; qd : OUT INTEGER RANGE 0 TO 255; qe : OUT INTEGER RANGE 0 TO 255; qf : OUT INTEGER RANGE 0 TO 255; qg : OUT INTEGER RANGE 0 TO 255; qh : OUT INTEGER RANGE 0 TO 255; qi : OUT INTEGER RANGE 0 TO 255;
上传时间： 2014-11-30
上传用户：半熟1994
This Application Note covers the basics of how to use Verilog as applied to ComplexProgrammable Logic Devices. Various combinational logic circuit examples, such asmultiplexers, decoders, encoders, comparators and adders are provided. Synchronous logiccircuit examples, such as counters and state machines are also provided.
上传时间： 2013-11-11
上传用户：y13567890
各种功能的计数器实例（VHDL源代码）:ENTITY counters IS PORT ( d : IN INTEGER RANGE 0 TO 255; clk : IN BIT; clear : IN BIT; ld : IN BIT; enable : IN BIT; up_down : IN BIT; qa : OUT INTEGER RANGE 0 TO 255; qb : OUT INTEGER RANGE 0 TO 255; qc : OUT INTEGER RANGE 0 TO 255; qd : OUT INTEGER RANGE 0 TO 255; qe : OUT INTEGER RANGE 0 TO 255; qf : OUT INTEGER RANGE 0 TO 255; qg : OUT INTEGER RANGE 0 TO 255; qh : OUT INTEGER RANGE 0 TO 255; qi : OUT INTEGER RANGE 0 TO 255;
上传时间： 2013-10-09
上传用户：松毓336
vhdl程序源代码，包括Combinational Logic counters Shift Registers Memory State Machines Registers Systems ADC and DAC Arithmetic等
上传时间： 2013-12-26
上传用户：363186
Features • Compatible with MCS-51® Products • 8K Bytes of In-System Programmable (ISP) Flash Memory – Endurance: 1000 Write/Erase Cycles • 4.0V to 5.5V Operating Range • Fully Static Operation: 0 Hz to 33 MHz • Three-level Program Memory Lock • 256 x 8-bit Internal RAM • 32 Programmable I/O Lines • Three 16-bit Timer/counters • Eight Interrupt Sources • Full Duplex UART Serial Channel • Low-power Idle and Power-down Modes • Interrupt Recovery from Power-down Mode • Watchdog Timer • Dual Data Pointer • Power-off Flag
标签： 8226 Programmable Compatible In-System
上传时间： 2015-06-27
上传用户：dianxin61
The last step in training phase is refinement of the clusters found above. Although DynamicClustering counters all the basic k-means disadvantages, setting the intra-cluster similarity r may require experimentation. Also, a cluster may have a lot in common with another, i.e., sequences assigned to it are as close to it as they are to another cluster. There may also be denser sub-clusters within the larger ones.
标签： DynamicClusteri refinement Although clusters
上传时间： 2014-01-04
上传用户：watch100
