This GLib version 2.16.1. GLib is the low-level core library that forms the basis for projects such as GTK+ and GNOME. It provides…
browser core 技术资料
汇集 browser core 相关的电路原理图、PCB工程文件、单片机/FPGA源代码、数据手册与应用设计方案。
This paper shows the development of a 1024-point radix-4 FFT VHDL core for applications in hardware signal processing, targeting l…
I2C core code in Hardware descrption language so as enable a cpld/fpga to be programmed for specific
I2C core code in Hardware descrption language so as enable a cpld/fpga to be programmed for specific customized applications of ou…
一个基于VHDL 的简单8位CPU的IP core核心代码
The combinatorial core of the OVSF code assignment problem that arises in UMTS is to assign some nodes of a complete binary tree o…
This is is a bridge IP core to interface the Tensilica PIF bus protocol with the OpenCores WishBone.
This is is a bridge IP core to interface the Tensilica PIF bus protocol with the OpenCores WishBone. It currently supports single-…
USBHostSlave is a USB 1.1 host and Device IP core. – Supports full speed (12Mbps) and low speed (1.5Mbps) operation. – USB Device …
请把uCosII的文件放到Core文件夹下。 共有三个任务,A,B为定时调度。C通过键盘的ISR中发送消息到邮箱。 程序在优龙开发板上调试通过,用的uCosII是2.70版本。
我用过的verilog hdl写的SDRAM core源程序,经过测试应用
M*core开发库文件,能够大大减轻开发者的难度