Wishbone
共 42 篇文章
Wishbone 相关的电子技术资料，包括技术文档、应用笔记、电路设计、代码示例等，共 42 篇文章，持续更新中。
Enhanced version of the Serial Peripheral Interface available on Motorola s MC68HC11 family of CPUs.
Enhanced version of the Serial Peripheral Interface available on Motorola s MC68HC11 family of CPUs.Enhancements include a wider supported operating frequency range, 4deep read and write fifos, and pr
本文主要介绍和分析了在集成芯片设计中几种常用的片上系统总线－CoreConnect 总线、MBA 总线、Wishbone 总线和OCP 总线
本文主要介绍和分析了在集成芯片设计中几种常用的片上系统总线－CoreConnect 总线、MBA 总线、Wishbone 总线和OCP 总线，通过比较这些总线的特性及适用范围，展望了它们的发展前景。
// -*- Mode: Verilog -*- // Filename : wb_master.v // Description : Wishbone Master Behavorial //
// -*- Mode: Verilog -*-
// Filename : wb_master.v
// Description : Wishbone Master Behavorial
// Author : Winefred Washington
// Created On : 2002 12 24
// Last Modified By: .
// Last Modified
SD卡控制器IP. 兼容SD卡协议2.0。与wishbone bus 接口
SD卡控制器IP. 兼容SD卡协议2.0。与wishbone bus 接口，方便与其他IP连接使用。
soc中ip核集成时所采用的一种片上总线
soc中ip核集成时所采用的一种片上总线，开发的，为opencores所采用，wishbone片上总线指南
-- WISHBONE revB2 compiant I2C master core -- -- author: Richard Herveille -- rev. 0.1 based on s
-- WISHBONE revB2 compiant I2C master core
--
-- author: Richard Herveille
-- rev. 0.1 based on simple_i2c
-- rev. 0.2 april 27th 2001, fixed incomplete sensitivity list on assign_dato process (th
USBHostSlave is a USB 1.1 host and Device IP core. – Supports full speed (12Mbps) and low speed (1.
USBHostSlave is a USB 1.1 host and Device IP core.
– Supports full speed (12Mbps) and low speed (1.5Mbps) operation.
– USB Device has four endpoints, each with their own independent FIFO.
– Support
This project features a full-hardware sound compressor using the well known algorithm: IMA ADPCM.
This project features a full-hardware sound compressor using the well known algorithm: IMA ADPCM.
The core acts as a slave WISHBONE device.
The output is perfectly compatible with any sound play
SoC-Wishbone System IP核的VHDL语言源代码
SoC-Wishbone System IP核的VHDL语言源代码，需要的开发环境是QUARTUS II 6.0。
This a state-machine driven rs232 serial port interface to a "Wishbone" // type of bus.
This a state-machine driven rs232 serial port interface to a "Wishbone"
// type of bus.
wishbone总线的VHDL源代码 wishbone适用于与FPGA中IP核的高速通信
wishbone总线的VHDL源代码
wishbone适用于与FPGA中IP核的高速通信，其接口简单，速度快 成为ip通信的主流
Wishbone dma ip core
Wishbone dma ip core
spi wishbone bus code
spi wishbone bus code
ethernet wishbone interface
ethernet wishbone interface
wishbone 源代码
wishbone 源代码，opencore
i2c VHDL,能够实现I2C 用的是wishbone总线
i2c VHDL,能够实现I2C 用的是wishbone总线
Wishbone 和 USB总线结构的介绍
Wishbone 和 USB总线结构的介绍
This is is a bridge IP core to interface the Tensilica PIF bus protocol with the OpenCores WishBone.
This is is a bridge IP core to interface the Tensilica PIF bus protocol with the OpenCores WishBone. It currently supports single-cycle as well as burst transfer operations. The core has been tested i
This demo shows how to use MATLAB, Optimization Toolbox, and Genetic Algorithm and Direct Search Too
This demo shows how to use MATLAB, Optimization Toolbox, and Genetic Algorithm and Direct Search Toolbox to optimize the design of a double wishbone suspension system.
opencore ahb to wishbone bus verilog code
opencore ahb to wishbone bus verilog code