📚 Wishbone技术资料

📦 资源总数：37

💻 源代码：790

🔌 电路图：1

Wishbone总线最先是由Silicore公司提出，己被移交给OpenCores组织维护，它通过在IP核之间建立一个通用接口完成互连。可以用于在软核、固核以及硬核之间进行互联。

🔥 Wishbone热门资料

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wishbone总线的VHDL源代码 wishbone适用于与FPGA中IP核的高速通信

wishbone总线的VHDL源代码 wishbone适用于与FPGA中IP核的高速通信，其接口简单，速度快成为ip通信的主流...

📅 2014-01-09 👤 maizezhen

wishbone VHDL FPGA IP核

VHDL MAC wishbone VHDL MAC wishbone

VHDL MAC wishbone VHDL MAC wishbone...

📅 2017-04-12 👤 亚亚娟娟123

wishbone VHDL MAC

opencore ahb to wishbone bus verilog code

opencore ahb to wishbone bus verilog code...

📅 2013-12-07 👤 努力努力再努力

opencore wishbone verilog code

Wishbone to LPC (Low-Pin Count) Bridge, includes master and slave modules. Supports 8-bit I/O Read a

Wishbone to LPC (Low-Pin Count) Bridge, includes master and slave modules. Supports 8-bit I/O Read and Write cycles, 8-bit Memory Read/Write cycles, D...

📅 2014-12-20 👤 古谷仁美

Wishbone Supports includes Low-Pin

This is is a bridge IP core to interface the Tensilica PIF bus protocol with the OpenCores WishBone.

This is is a bridge IP core to interface the Tensilica PIF bus protocol with the OpenCores WishBone. It currently supports single-cycle as well as bur...

📅 2013-12-21 👤 gonuiln

Tensilica OpenCores interface the

💻 Wishbone源代码

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wb_dma_wb_mast.v

sd_controller_top_tb.v

sd_controller_top.v

i2c_master_defines.v

i2c_master_defines.v

📂 Wishbone资料分类

🔥 热门资料查看最受欢迎的资源 💻 源代码程序代码与工程文件 🔌 电路图原理图PCB布局 📚 全部资料 37 个资源