wishbone_slave_unit.wishbone_slave.c_state.txt

来自「这是用pci-wishbone核和16450串口核在xilinx的fpga上实现」· 文本 代码 · 共 30 行

indata[0] = 19'b1000000000000000000 ; outdata[0] = 6'b000001; 
indata[1] = 19'b0000000000000000000 ; outdata[1] = 6'b000001; 
indata[2] = 19'b1000000000000000111 ; outdata[2] = 6'b000001; 
indata[3] = 19'b0000000000000000111 ; outdata[3] = 6'b000010; 
indata[4] = 19'b0000000000000000000 ; outdata[4] = 6'b000001; 
indata[5] = 19'b1000000000000000111 ; outdata[5] = 6'b000001; 
indata[6] = 19'b0000000000000000111 ; outdata[6] = 6'b000010; 
indata[7] = 19'b0000001000000101110 ; outdata[7] = 6'b000100; 
indata[8] = 19'b0000000000000000000 ; outdata[8] = 6'b000001; 
indata[9] = 19'b1000000000000000111 ; outdata[9] = 6'b000001; 
indata[10] = 19'b0000000000000000111 ; outdata[10] = 6'b000010; 
indata[11] = 19'b0000001000000101110 ; outdata[11] = 6'b000100; 
indata[12] = 19'b0000000010000000010 ; outdata[12] = 6'b000100; 
indata[13] = 19'b1000000000000000111 ; outdata[13] = 6'b000001; 
indata[14] = 19'b0000000000000000111 ; outdata[14] = 6'b000010; 
indata[15] = 19'b0000010000000100110 ; outdata[15] = 6'b001000; 
indata[16] = 19'b0000000000000000000 ; outdata[16] = 6'b000001; 
indata[17] = 19'b1000000000000000111 ; outdata[17] = 6'b000001; 
indata[18] = 19'b0000000000000000111 ; outdata[18] = 6'b000010; 
indata[19] = 19'b0000010000000100110 ; outdata[19] = 6'b001000; 
indata[20] = 19'b0000000010000001010 ; outdata[20] = 6'b001000; 
indata[21] = 19'b1000000000000000111 ; outdata[21] = 6'b000001; 
indata[22] = 19'b0000000000000000111 ; outdata[22] = 6'b000010; 
indata[23] = 19'b0000000000000011110 ; outdata[23] = 6'b010000; 
indata[24] = 19'b0000000000000000000 ; outdata[24] = 6'b000001; 
indata[25] = 19'b1000000000000000111 ; outdata[25] = 6'b000001; 
indata[26] = 19'b0000000000000000111 ; outdata[26] = 6'b000010; 
indata[27] = 19'b0000000000000010110 ; outdata[27] = 6'b100000; 
indata[28] = 19'b0000000000000000000 ; outdata[28] = 6'b000001;