VERILOG
VerilogHDL是一种硬件描述语言，以文本形式来描述数字系统硬件的结构和行为的语言，用它可以表示逻辑电路图、逻辑表达式，还可以表示数字逻辑系统所完成的逻辑功能。VerilogHDL和VHDL是世界上最流行的两种硬件描述语言，都是在20世纪80年代中期开发出来的。前者由GatewayDesignA...
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用Verilog实现的贪吃蛇游戏(基于FPGA开发板)讲解
该文档为用Verilog实现的贪吃蛇游戏(基于FPGA开发板)讲解文档，是一份很不错的参考资料，具有较高参考价值，感兴趣的可以下载看看………………...
这是我个人写的DLX处理器流水线的Verilog代码
这是我个人写的DLX处理器流水线的Verilog代码，在ModelSim中仿真通过，并且在ISE中能综合！即可以下载到FPGA中运行指令，指令可以根据需要定义，也可和相应的编译器配合使用，这里给学习流...
it is a verilog code written for MAX1886 ADC interin modelsim simulator and it will synthesize in x
it is a verilog code written for MAX1886 ADC interin modelsim simulator and it will synthesize in x...
it is a verilog code written for digital watch in modelsim simulator and it will synthesize in xin
it is a verilog code written for digital watch in modelsim simulator and it will synthesize in xin...
it is a verilog code written for MELAY state machine based UART and it wll synthesize in xinlix
it is a verilog code written for MELAY state machine based UART and it wll synthesize in xinlix ...