这是一个FPGA的实验源码，可以实现对一段音乐的播放。用Verilog语言编写的，对初学者会有一定的帮助。
上传时间： 2013-09-01
上传用户：13215175592
采用Verilog语言,实现了FPGA控制视频芯片的数据采集,并将数据按帧存储起来
上传时间： 2013-09-01
上传用户：喵米米米
pc104接口的verilog代码，仅供参考
上传时间： 2013-09-03
上传用户：chukeey
结合XILINXCPLD所做的模拟RS232通信verilog源程序
标签： XILINXCPLD verilog 232 RS
上传时间： 2013-09-03
上传用户：gps6888
这是一段控制1394芯片的cpld的verilog程序,可以参考,在实际项目中已经采用.
上传时间： 2013-09-04
上传用户：pkkkkp
i2c code for the verilog
上传时间： 2013-09-04
上传用户：DXM35
Cadence guide for verilog
上传时间： 2013-09-04
上传用户：123454
Cadence Verilog Language and Simulation
标签： Simulation Language Cadence Verilog
上传时间： 2013-09-06
上传用户：yl1140vista
In this paper, we discuss efficient coding and design styles using verilog. This can beimmensely helpful for any digital designer initiating designs. Here, we address different problems rangingfrom RTL-Gate Level simulation mismatch to race conditions in writing behavioral models. All theseproblems are accompanied by an example to have a better idea, and these can be taken care off if thesecoding guidelines are followed. Discussion of all the techniques is beyond the scope of this paper, however,here we try to cover a few of them.
标签： Efficient Verilog Digital Coding
上传时间： 2013-11-22
上传用户：han_zh
One of the most misunderstood constructs in the Verilog language is the nonblockingassignment. Even very experienced Verilog designers do not fully understand how nonblockingassignments are scheduled in an IEEE compliant Verilog simulator and do not understand whenand why nonblocking assignments should be used. This paper details how Verilog blocking andnonblocking assignments are scheduled, gives important coding guidelines to infer correctsynthesizable logic and details coding styles to avoid Verilog simulation race conditions
上传时间： 2013-10-17
上传用户：tb_6877751
