Static+PLL全部资料 - 虫虫开发者社区

·摘要：  介绍了一种用于DSP内嵌锁相环的低功耗、高线性CMOS压控环形振荡器.电路采用四级延迟单元来获得相位相差90.的正交输出时钟,每级采用调节电流源大小,改变电容放电速度的方式.基于SMIC 0.35μm CMOS工艺模型...

2024-08-30 4 Static+PLL

CMOS PLL Synthesizers：analysis and design -- a very good book by Keliu Shu Edgar Sánchez-Sinencio and published by Spri...

2013-12-24 106 Static+PLL

Jitter is extremely important in systems using PLL-based clock drivers. The effects of jitter range from not having any...

2014-11-25 117 Static+PLL

％The phase locked loop(PLL),adjusts the phase of a local oscillator ％w.r.t the incoming modulated signal.In this way,t...

2015-09-28 121 Static+PLL

基于CD4046构成的PLL及应用 CD4046构成的PLL在通信、频率处理、自动控制等技术领域中应用较为广泛，正确理解CD4046对掌握电路基本组成、原理及应用。对处理实际工程问题有很大帮助

2014-01-17 77 Static+PLL

ADF4350/1系列是什么？

2013-12-27 182 Static+PLL

DDS（直接数字频率合成）技术是一门在频率合成领域的新兴技术，具有响应时间短，精度高等优点。而PLL（Phase Locked Loop）锁相环技术虽然工作速度慢，但稳定可靠。VXI 总线具有

2024-03-19 1 Static+PLL

A new PLL topology and a new simplified linear model are presented. The new fractional-N synthesizer presents no referen...

2016-04-14 193 Static+PLL

2015-06-15 138 Static+PLL

2014-01-11 38 Static+PLL

Static+PLL