基于FPGA的10M/100M以太网控制器的设计
介绍了一种10M/ 100M 以太网控制器的实现方法,该控制器以FIFO 作为帧缓存,通过程序设计实现10M/ 100M 自适应,设计中采用WS 接口,提高了设计的灵活行,可以实现与其他SOC 的互连[1 ] ,该设计采用VerilogHDL 硬件描述语言编程,基于ISE 开发环境,在Xilinx ...
介绍了一种10M/ 100M 以太网控制器的实现方法,该控制器以FIFO 作为帧缓存,通过程序设计实现10M/ 100M 自适应,设计中采用WS 接口,提高了设计的灵活行,可以实现与其他SOC 的互连[1 ] ,该设计采用VerilogHDL 硬件描述语言编程,基于ISE 开发环境,在Xilinx ...
it is a verilog code written for digital watch in modelsim simulator and it will synthesize in xinlix ise 8.2i.i have tested it om my kit.[i mae my ...
it is a verilog code written for FIFO in modelsim simulator and it will synthesize in xinlix ise 8.2i.i have tested it om my kit.[i mae my own kit f...
it is a verilog code written for traffic light controller will synthesize in xinlix ise 8.2i.i have tested it om my kit.[i mae my own kit for spartan...
it is a verilog code written for MELAY state machine based UART and it wll synthesize in xinlix ise 8.2i.i have tested it om my kit.[i mae my own ...