library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity counter is Port ( clk : in std_logic; resetn : in std_logic; dout : out std_logic_vector(7 downto 0); lcd_en : out std_logic; lcd_rs : out std_logic; lcd_rw : out std_logic); end counter;
上传时间： 2013-10-30
上传用户：wqxstar
MAXQUSBJTAGOW评估板软件:关键特性 Easily Load and Debug Code Interface Provides In-Application Debugging Features Step-by-Step Execution Tracing Breakpointing by Code Address, Data Memory Address, or Register Access Data Memory View and Edit Supports Logic Levels from 1.1V to 3.6V Supports JTAG and 1-Wire Protocols Each Adapter Has Its Own Unique Serial ID, Allowing Multiple Adapters to be Connected Without COM Port Conflicts Has In-Field Upgradable Capability if Firmware Needs to be Upgraded Enclosure Protects from Shorts and ESD
标签： MAXQUSBJTAGOW 评估板 软件
上传时间： 2013-10-24
上传用户：teddysha
虚拟串口软件
标签： Virtual Serial Driver Port
上传时间： 2013-10-27
上传用户：1234321@q
Port1.0 使用说明 Port1.0是作者本人在进行电子制作和维修过程中萌发的一个思路。在电子制作、维修中，经常要用到多路的脉冲信号或是要测量多路的脉冲信号。本软件可通过微机并口向用户提供多达12路的标准TTL脉冲信号，同时可进行5路的标准TTL脉冲信号的波形显示。 软件的使用方法极为简单。输出信号时，只要选中或取消引脚号，就能在相应的引脚得到相应的脉冲信号（统一为选中为高电平，取消为低电平），“清零”按钮为对应该组的所有信号清零。 输入信号的波形显示，按“开始”按钮为开始进行显示，“停止”为暂停。 在设置面板中，“数据读入时间间隔”为读入时间的设定。“并行打印端口设置”为显示微机中存在的可用打印端口，并可以设定本软件当前要使用的端口（如只有一个可用端口，就为缺省端口，如有多个可用端口软件自动选择最后一个可用端口为当前使用端口）。 本软件的输入波形显示没有运用VXD等的技术支持，在速度上不能做到高频的实时性，只能用在低速的环境下。这个版本没有提供多数据的连续输出。这些问题在下一个版本中得到改进和支持。 本软件可使用在微机的打印适配器、打印机等各种的并口设备检修中，还可用在各种数字电路、单片机的制作和维修中。在下一版本在这方面会有更大的支持。 * 注意：只支持win9x * 注意：并口的输入/输出电平为0－5伏TTL，不能连接高电压高电流的电路，以免埙坏主板或打印适配器。要连接COMS的0－12伏时请用户自做转换电路再连接。 * 注意：在使用本软件时最好不要同时使用打印机之类的并口设备。如本程序已运行请先关闭，再使用并口设备。
上传时间： 2014-04-18
上传用户：paladin
MAXQUSBJTAGOW评估板软件:关键特性 Easily Load and Debug Code Interface Provides In-Application Debugging Features Step-by-Step Execution Tracing Breakpointing by Code Address, Data Memory Address, or Register Access Data Memory View and Edit Supports Logic Levels from 1.1V to 3.6V Supports JTAG and 1-Wire Protocols Each Adapter Has Its Own Unique Serial ID, Allowing Multiple Adapters to be Connected Without COM Port Conflicts Has In-Field Upgradable Capability if Firmware Needs to be Upgraded Enclosure Protects from Shorts and ESD
标签： MAXQUSBJTAGOW 评估板 软件
上传时间： 2013-11-23
上传用户：truth12
虚拟串口软件
标签： Virtual Serial Driver Port
上传时间： 2013-10-23
上传用户：JIUSHICHEN
通过以太网远程配置Nios II 处理器 应用笔记 Firmware in embedded hardware systems is frequently updated over the Ethernet. For embedded systems that comprise a discrete microprocessor and the devices it controls, the firmware is the software image run by the microprocessor. When the embedded system includes an FPGA, firmware updates include updates of the hardware image on the FPGA. If the FPGA includes a Nios® II soft processor, you can upgrade both the Nios II processor—as part of the FPGA image—and the software that the Nios II processor runs, in a single remote configuration session.
上传时间： 2013-11-22
上传用户：chaisz
使用Nios II紧耦合存储器教程 Chapter 1. Using Tightly Coupled Memory with the Nios II Processor Reasons for Using Tightly Coupled Memory . . . . . . . . . . . . . . . . . . . . . . . 1–1 Tradeoffs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1 Guidelines for Using Tightly Coupled Memory . . . .. . . . . . . . 1–2 Hardware Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2 Software Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . 1–3 Locating Functions in Tightly Coupled Memory . . . . . . . . . . . . . 1–3 Tightly Coupled Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–4 Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–4 Dual Port Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . 1–5 Building a Nios II System with Tightly Coupled Memory . . . . . . . . . . . 1–5
上传时间： 2013-10-13
上传用户：黄婷婷思密达
Nios II定制指令用户指南：With the Altera Nios II embedded processor, you as the system designer can accelerate time-critical software algorithms by adding custom instructions to the Nios II processor instruction set. Using custom instructions, you can reduce a complex sequence of standard instructions to a single instruction implemented in hardware. You can use this feature for a variety of applications, for example, to optimize software inner loops for digital signal processing (DSP), packet header processing, and computation-intensive applications. The Nios II configuration wizard,part of the Quartus® II software’s SOPC Builder, provides a graphical user interface (GUI) used to add up to 256 custom instructions to the Nios II processor. The custom instruction logic connects directly to the Nios II arithmetic logic unit (ALU) as shown in Figure 1–1.
上传时间： 2013-10-12
上传用户：kang1923
Abstract: This application note discusses the development and deployment of 3G cellular femtocell base stations. The technicalchallenges for last-mile residential connectivity and adding system capacity in dense urban environments are discussed, with 3Gfemtocell base stations as a cost-effective solution. Maxim's 3GPP TS25.104-compliant transceiver solution is presented along withcomplete radio reference designs such as RD2550. For more information on the RD2550, see reference design 5364, "FemtocellRadio Reference Designs Using the MAX2550–MAX2553 Transceivers."
标签： Base-Station Applications Single-Chip Transceiver
上传时间： 2013-11-05
上传用户：超凡大师
