源码文件
#!/bin/sh # used for energy study with enough energy # one mobility mode, random change distribution of traffic source for proto …
Run+Level 源代码
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源码文件
#!/usr/bin/perl -w -U # # Possible improvements: # # - distinguish stdout and stderr output # - add environment variable like ass…
源码文件
#!/bin/csh set i2c = ../../../.. set bench = $i2c/bench set wave_dir = $i2c/sim/rtl_sim/i2c_verilog/waves ncverilog …
源码文件
#!/bin/sh # used for energy study with enough energy # one mobility mode, random change distribution of traffic source for proto …
源码文件
#!/bin/sh CLICKPATH=. /usr/local/click/bin/click < xorp.click
源码文件
#!/bin/csh set i2c = ../../../.. set bench = $i2c/bench set wave_dir = $i2c/sim/rtl_sim/i2c_verilog/waves ncverilog …
源码文件
#!/bin/csh set i2c = ../../../.. set bench = $i2c/bench set wave_dir = $i2c/sim/rtl_sim/i2c_verilog/waves ncverilog …
源码文件
verilog res_acs.v res_stage.v MS_res_ACS1_0.v MS_res_ACS1_1.v MS_res_ACS2_0.v \ MS_res_ACS2_1.v MS_res_stage.v backtrack.v…
源码文件
verilog res_acs.v res_stage.v MS_res_ACS1_0.v MS_res_ACS1_1.v MS_res_ACS2_0.v \ MS_res_ACS2_1.v MS_res_stage.v backtrack.v…
源码文件
verilog res_acs.v res_stage.v MS_res_ACS1_0.v MS_res_ACS1_1.v MS_res_ACS2_0.v \ MS_res_ACS2_1.v MS_res_stage.v backtrack.v…