run

viterbi译码器的一种fpga实现

verilog res_acs.v res_stage.v MS_res_ACS1_0.v MS_res_ACS1_1.v MS_res_ACS2_0.v \
        MS_res_ACS2_1.v MS_res_stage.v backtrack.v \
        acs1_0.v acs1_1.v acs2_0.v acs2_1.v stage.v block.v decoder.v top.v