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Read-and-Write

  • at24c16 c程序

    一个24c16的读写程序(已经调试过)(arens)  //////////////////////////////////////////////////////////////// //24c16读写驱动程序,FM24C16A-AT24C16中文资料pdf //=-------------------------------------------------------------------------------/*模块调用:读数据:read(unsigned int address)写数据:write(unsigned int address,unsigned char dd)   dd为要写的 数据字节*///---------------------------------------------------------------------------------- sbit sda=P3^0;sbit scl=P3^1; sbit a0=ACC^0;                  //定义ACC的位,利用ACC操作速度最快sbit a1=ACC^1;sbit a2=ACC^2;sbit a3=ACC^3;sbit a4=ACC^4;sbit a5=ACC^5;sbit a6=ACC^6;sbit a7=ACC^7; //--------------------------------------------------------------------------------------#pragma disablevoid s24(void)                 //起始函数{_nop_();    scl=0;     sda=1;    scl=1;    _nop_();    sda=0;    _nop_();    _nop_();    scl=0;     _nop_();    _nop_();    sda=1;

    标签: 24c c16 at 24

    上传时间: 2013-10-31

    上传用户:fdfadfs

  • 2120+2025L lehua write乐华烧录工具加全部程序

    2120+2025L lehua write乐华烧录工具加全部程序 希望大家喜欢。

    标签: lehua write 2120 2025

    上传时间: 2013-11-01

    上传用户:aa7821634

  • 2120+2025L lehua write乐华烧录工具加全部程序

    2120+2025L lehua write乐华烧录工具加全部程序 希望大家喜欢。

    标签: lehua write 2120 2025

    上传时间: 2013-12-10

    上传用户:xingyuewubian

  • PCB Design Considerations and Guidelines for 0.4mm and 0.5mm WLPs

    Abstract: Using a wafer-level package (WLP) can reduce the overall size and cost of your solution.However when using a WLP IC, the printed circuit board (PCB) layout can become more complex and, ifnot carefully planned, result in an unreliable design. This article presents some PCB designconsiderations and general recommendations for choosing a 0.4mm- or 0.5mm-pitch WLP for yourapplication.

    标签: Considerations Guidelines and Design

    上传时间: 2013-11-09

    上传用户:ls530720646

  • PADS-PowerLogic and PowerPcb实用教程

    PADS-PowerLogic and PowerPcb实用教程

    标签: PADS-PowerLogic PowerPcb and 实用教程

    上传时间: 2014-01-24

    上传用户:qiaoyue

  • XAPP740利用AXI互联设计高性能视频系统

    This application note covers the design considerations of a system using the performance features of the LogiCORE™ IP Advanced eXtensible Interface (AXI) Interconnect core. The design focuses on high system throughput through the AXI Interconnect core with F MAX  and area optimizations in certain portions of the design. The design uses five AXI video direct memory access (VDMA) engines to simultaneously move 10 streams (five transmit video streams and five receive video streams), each in 1920 x 1080p format, 60 Hz refresh rate, and up to 32 data bits per pixel. Each VDMA is driven from a video test pattern generator (TPG) with a video timing controller (VTC) block to set up the necessary video timing signals. Data read by each AXI VDMA is sent to a common on-screen display (OSD) core capable of multiplexing or overlaying multiple video streams to a single output video stream. The output of the OSD core drives the DVI video display interface on the board. Performance monitor blocks are added to capture performance data. All 10 video streams moved by the AXI VDMA blocks are buffered through a shared DDR3 SDRAM memory and are controlled by a MicroBlaze™ processor. The reference system is targeted for the Virtex-6 XC6VLX240TFF1156-1 FPGA on the Xilinx® ML605 Rev D evaluation board

    标签: XAPP 740 AXI 互联

    上传时间: 2013-11-23

    上传用户:shen_dafa

  • USB接口控制器参考设计,xilinx提供VHDL代码 us

    USB接口控制器参考设计,xilinx提供VHDL代码 usb xilinx vhdl ;  This program is free software; you can redistribute it and/or modify ;  it under the terms of the GNU General Public License as published by ;  the Free Software Foundation; either version 2 of the License, or ;  (at your option) any later version. ;      ;  This program is distributed in the hope that it will be useful, ;  but WITHOUT ANY WARRANTY; without even the implied warranty of ;  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the ;  GNU General Public License for more details. ;      ;  You should have received a copy of the GNU General Public License ;  along with this program; if not, write to the Free Software ;  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.

    标签: xilinx VHDL USB us

    上传时间: 2013-10-29

    上传用户:zhouchang199

  • 高精度温度测量铂电阻温度探测器(PRTDs)和​​ADC

    Abstract: Many modern industrial, medical, and commercial applications require temperature measurements in the extended temperature rangewith accuracies of ±0.3°C or better, performed with reasonable cost and often with low power consumption. This article explains how platinumresistance temperature detectors (PRTDs) can perform measurements over wide temperature ranges of -200°C to +850°C, with absolute accuracyand repeatability better than ±0.3°C, when used with modern processors capable of resolving nonlinear mathematical equation quickly and costeffectively. This article is the second installment of a series on PRTDs. For the first installment, please read application note 4875, "High-Accuracy Temperature Measurements Call for Platinum Resistance Temperature Detectors (PRTDs) and Precision Delta-Sigma ADCs."

    标签: PRTDs ADC 高精度 温度测量

    上传时间: 2013-11-06

    上传用户:WMC_geophy

  • Transfer Files to and from an FTP Server

    Transfer Files to and from an FTP Server

    标签: Transfer Server Files from

    上传时间: 2013-12-17

    上传用户:jing911003

  • ComPort Library是一套用来编写串口通讯程序的控件。它包含5个控件:TComPort, TComDataPacket, TComComboBox, TComRadioGroup and T

    ComPort Library是一套用来编写串口通讯程序的控件。它包含5个控件:TComPort, TComDataPacket, TComComboBox, TComRadioGroup and TComLed。利用这些工具(当然还有DELPHI开发环境),你能更快更简单地开发串口通讯程序。包含Delphi上下文相关的帮助文件和源代码(4000行)。功能无限制。源代码:包含。适用语言:CB3 CB4 CB5 D3 D4 D5

    标签: TComDataPacket TComRadioGroup TComComboBox TComPort

    上传时间: 2015-01-05

    上传用户:363186