implemention of FPGA and DSP linking port, using Asynchronous mode
implemention of FPGA and DSP linking port, using Asynchronous mode...
implemention of FPGA and DSP linking port, using Asynchronous mode...
Cadence Verilog Language and Simulation...
cadence material includes caden_layout,CADENCE_20Manual,cs5710-layout1x2 and manual...
Can convert data file(txt format)to CAD(scr)file,and draw curve!...
proteus and keil 两者联合实现Max7221动态显示,解决一些初学者对proteus and keil如何实现的困惑;...