同步技术是跳频通信系统的关键技术之一，尤其是在快速跳频通信系统中，常规跳频通信通过同步字头携带相关码的方法来实现同步，但对于快跳频来说，由于是一跳或者多跳传输一个调制符号，难以携带相关码。对此引入双跳频图案方法，提出了一种适用于快速跳频通信系统的同步方案。采用短码携带同步信息，克服了快速跳频难以携带相关码的困难。分析了同步性能，仿真结果表明该方案同步时间短、虚警概率低、捕获概率高，同步性能可靠。 Abstract: Synchronization is one of the key techniques to frequency-hopping communication system， especially in the fast frequency hopping communication system. In conventional frequency hopping communication systems， synchronization can be achieved by synchronization-head which can be used to carry the synchronization information， but for the fast frequency hopping， Because modulation symbol is transmitted by per hop or multi-hop， it is difficult to carry the correlation code. For the limitation of fast frequency hopping in carrying correlation code， a fast frequency-hopping synchronization scheme with two hopping patterns is proposed. The synchronization information is carried by short code， which overcomes the difficulty of correlation code transmission in fast frequency-hopping. The performance of the scheme is analyzed， and simulation results show that the scheme has the advantages of shorter synchronization time， lower probability of false alarm， higher probability of capture and more reliable of synchronization.
上传时间： 2013-11-23
上传用户：mpquest
The information in this specification is subject to change without notice.Use of this specification for product design requires an executed license agreement from the CompactFlashAssociation.The CompactFlash Association shall not be liable for technical or editorial errors or omissions contained herein; norfor incidental or consequential damages resulting from the furnishing, performance, or use of this material.All parts of the CompactFlash Specification are protected by copyright law and all rights are reserved. Thisdocumentation may not, in whole or in part, be copied, photocopied, reproduced, translated, or reduced to anyelectronic medium or machine readable form without prior consent, in writing, from the CompactFlash Association.The CFA logo is a trademark of the CompactFlash Association.Product names mentioned herein are for identification purposes only and may be trademarks and/or registeredtrademarks of their respective companies.© 1998-99, CompactFlash Association. All rights reserved.
标签： 技术资料
上传时间： 2013-10-08
上传用户：stewart·
On the LPC13xx, programming, erasure and re-programming of the on-chip flash can be performed using In-System Programming (ISP) via the UART serial port, and also, can be performed using In-Application Programming (IAP) calls directed by the end-user code. For In-System Programming (ISP) via the UART serial port, the ISP command handler (resides in the bootloader) allows erasure of one or more sector (s) of the on-chip flash memory.
上传时间： 2013-12-13
上传用户：lmq0059
The NXP LPC315x combine an 180 MHz ARM926EJ-S CPU core, High-speed USB 2.0OTG, 192 KB SRAM, NAND flash controller, flexible external bus interface, an integratedaudio codec, Li-ion charger, Real-Time Clock (RTC), and a myriad of serial and parallelinterfaces in a single chip targeted at consumer, industrial, medical, and communicationmarkets. To optimize system power consumption, the LPC315x have multiple powerdomains and a very flexible Clock Generation Unit (CGU) that provides dynamic clockgating and scaling.The LPC315x is implemented as multi-chip module with two side-by-side dies, one fordigital fuctions and one for analog functions, which include a Power Supply Unit (PSU),audio codec, RTC, and Li-ion battery charger.
上传时间： 2014-01-17
上传用户：Altman
本软件是关于MAX338, MAX339的英文数据手册：MAX338, MAX339 8通道/双4通道、低泄漏、CMOS模拟多路复用器 The MAX338/MAX339 are monolithic, CMOS analog multiplexers (muxes). The 8-channel MAX338 is designed to connect one of eight inputs to a common output by control of a 3-bit binary address. The dual, 4-channel MAX339 is designed to connect one of four inputs to a common output by control of a 2-bit binary address. Both devices can be used as either a mux or a demux. On-resistance is 400Ω max, and the devices conduct current equally well in both directions. These muxes feature extremely low off leakages (less than 20pA at +25°C), and extremely low on-channel leakages (less than 50pA at +25°C). The new design offers guaranteed low charge injection (1.5pC typ) and electrostatic discharge (ESD) protection greater than 2000V, per method 3015.7. These improved muxes are pin-compatible upgrades for the industry-standard DG508A and DG509A. For similar Maxim devices with lower leakage and charge injection but higher on-resistance, see the MAX328 and MAX329.
上传时间： 2013-11-12
上传用户：18711024007
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity counter is Port ( clk : in std_logic; resetn : in std_logic; dout : out std_logic_vector(7 downto 0); lcd_en : out std_logic; lcd_rs : out std_logic; lcd_rw : out std_logic); end counter;
上传时间： 2013-10-30
上传用户：wqxstar
This example provides a description of how to use the USART with hardware flowcontrol and communicate with the Hyperterminal.First, the USART2 sends the TxBuffer to the hyperterminal and still waiting fora string from the hyperterminal that you must enter which must end by '\r'character (keypad ENTER button). Each byte received is retransmitted to theHyperterminal. The string that you have entered is stored in the RxBuffer array. The receivebuffer have a RxBufferSize bytes as maximum. The USART2 is configured as follow: - BaudRate = 115200 baud - Word Length = 8 Bits - One Stop Bit - No parity - Hardware flow control enabled (RTS and CTS signals) - Receive and transmit enabled - USART Clock disabled - USART CPOL: Clock is active low - USART CPHA: Data is captured on the second edge - USART LastBit: The clock pulse of the last data bit is not output to the SCLK pin
上传时间： 2013-10-31
上传用户：yy_cn
C++在几乎所有的计算环境中都非常普及，而且可以用于几乎所有的应用程序。C++从C中继承了过程化编程的高效性，并集成了面向对象编程的功能。C++在其标准库中提供了大量的功能。有许多商业C++库支持数量众多的操作系统环境和专业应用程序。但因为它的内容太多了，所以掌握C++并不十分容易。本书详述了C++语言的各个方面，包括数据类型、程序控制、函数、指针、调试、类、重载、继承、多态性、模板、异常和输入输出等内容。每一章都以前述内容为基础，每个关键点都用具体的示例进行详细的讲解。本书基本不需要读者具备任何C++知识，书中包含了理解C++的所有必要知识，读者可以从头开始编写自己的C++程序。本书也适合于具备另一种语言编程经验但希望全面掌握C++语言的读者。 I created all the files under Microsoft Windows so lines are terminated by CR/LF. In addition to this "ReadMe" file you will find three zip archives in the primary archive, so you need to unzip each of these to get at the code. 为PDG格式,这有pdg阅读器下载|pdg文件阅读器下载
标签： 源代码
上传时间： 2013-11-18
上传用户：gaoqinwu
superpro 3000u 驱动 PIC16C65B@QFP44 [SA245] PIC16C65B: Part number QFP44: Package in QFP44 SA245: Adapter purchase number AM29DL320GT@FBGA48 [SA642+B026] AM29DL320GT: Part number FBGA48: Package in FBGA48 SA642: Adapter purchase number (Top board with socket) B026: Adapter purchase number (Bottom board, exchangable for different parts) 87C196CA@PLCC68(universal adapter) [PEP+S414T] 87C196CA: Part number PLCC68: Package in PLCC68 universal adapter: this adapter is valid for all parts in this package PEP: The PEP (Pin-driver Expansion Pack necessary to work with the adapter S414T) S414T: Adapter purchase number (Universal for all parts in this package) S71PL127J80B@FBGA64(special adapter) [(SA642A-B079A-Y096AF001)] S71PL127J80B: Part number FBGA64: Package in FBGA64 special adapter: this adapter is valid for this
上传时间： 2013-10-23
上传用户：Avoid98
深入剖析赛灵思（Xilinx）All Programmable三大创新器件:赛灵思在 28nm 节点上推出的多种新技术为客户带来了重大的超前价值，并使赛灵思领先竞争对手整整一代。赛灵思并不是简单地将现有的 FPGA 架构迁移到新的技术节点上，而是力求引领多种 FPGA 创新，并率先推出了 All Programmable 3D IC 和 SoC。 今天推出的 All Programmable 产品采用了各种形式的可编程技术，包括可编程硬件和软件、数字信号和模拟混合信号（AMS）、单晶片和多片 3D IC 方案（图 1）。有了这些全新的 All Programmable 器件，设计团队就能进一步提升可编程系统的集成度，提高整体系统性能，降低 BOM 成本，并以更快的速度向市场推出更具创新性的智能产品。
标签： Programmable Xilinx All 赛灵思
上传时间： 2013-10-29
上传用户：1427796291
