源码文件
Build Log --------------------Configuration: MatrixCalculator - Win32 Debug-------------------- Command Lines Creating comm…
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源码文件
Release 6.2i - Bitgen G.28 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Loading device database for application Bit…
源码文件
WARNING:DesignRules:372 - Netcheck: Gated clock. Clock net U3_S1 is sourced by a combinatorial pin. This is not good design pr…
源码文件
Gated clock. Clock net main_00/top0/data_path0/dqs3_delayed_col1 is sourced by a combinatorial pin. This is not good design practi…
源码文件
Release 8.1i - Bitgen I.24 Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved. Loading device for application Rf_Device fro…
源码文件
WARNING:PhysDesignRules:372 - Gated clock. Clock net main_00/top0/data_path0/dqs3_delayed_col1 is sourced by a combinatorial p…
源码文件
WARNING:DesignRules:372 - Netcheck: Gated clock. Clock net XLXN_25 is sourced by a combinatorial pin. This is not good design …
源码文件
WARNING:DesignRules:372 - Netcheck: Gated clock. Clock net XLXI_10__n0001 is sourced by a combinatorial pin. This is not good …
源码文件
WARNING:DesignRules:372 - Netcheck: Gated clock. Clock net XLXI_8__n0010 is sourced by a combinatorial pin. This is not good d…
源码文件
WARNING:PhysDesignRules:372 - Gated clock. Clock net a0/_n0017 is sourced by a combinatorial pin. This is not good design prac…