AC220V转DC5V(3W )-RS485电路-继电器驱动板ALTIUM设计硬件原理图+PCB+AD集成封装库，2层板设计，大小为59x62mm，Altium Designer 设计的工程文件，包括完整的原理图及PCB文件，可以用Altium(AD)软件打开或修改，可作为你产品设计的参考。集成封装器件型号列表：Library Component Count : 20Name DESCRIPTION----------------------------------------------------------------------------------------------------CAP1 GRM21BR61A106KE19L，106,10μF,±10%,10V,X5R,0805,muRata,RoHSCON2 ConnectorCON3 ConnectorCON4 ConnectorDIODE ZENER2 SMBJ6.5CA,DO-214AA,君耀,RoHSDIODE1 1N4148,SOD-323,长电,RoHSFUSE1 MST2.50,T2.5A,250V,长方形,CONQUER,RoHSHEADER 5X2 HOLE - 不上螺丝 MARKER MAX485CSA SP485REN-L,SO-8,EXAR,RoHSNPN-1 9013,SOT-23,长电,RoHSRELAY-SPST HF46F/005-HS1,20.5×7.2×15.3mm,宏发,RoHSRES-PTC NTC,5D-9,DIP,RoHSRES2 10Ω,0603,*,RoHSRES4 471KD10,直插,君耀,RoHSZLGZY GAOYA ZY0IFBxxP-3W ZY0IGB05P-3W V1.00ZY_ESD-MARK
上传时间： 2021-12-21
上传用户：aben
黑金CYCLONE4 EP4CE6F17C8 FPGA开发板ALTIUM设计硬件工程（原理图+PCB+AD集成封装库）,Altium Designer 设计的工程文件，包括完整的原理图及PCB文件，可以用Altium(AD)软件打开或修改，可作为你产品设计的参考。集成封装器件型号列表：Library Component Count : 50Name DESCRIPTION----------------------------------------------------------------------------------------------------1117-3.3 24LC04B_0 4148 BAV99 CAP NP_Dup2CAP NP_Dup2_1 CAP NP_Dup2_2CP2102_0 C_Dup1 C_Dup1_1C_Dup2 C_Dup3 C_Dup4 C_Dup4_1 Circuit Breaker Circuit BreakerConnector 15 Receptacle Assembly, 15-Pin, Sim Line ConnectorDS1302_8SO EC EP4CE6F17C8 Cyclone IV Family FPGA, 2V Core, 179 I/O Pins, 2 PLLs, 256-Pin FBGA, Speed Grade 8, Commercial GradeEP4CE6F17C8_1 Cyclone IV Family FPGA, 2V Core, 179 I/O Pins, 2 PLLs, 256-Pin FBGA, Speed Grade 8, Commercial GradeFuse 2 FuseHEX6HY57651620/SO_0 Header 2 Header, 2-PinHeader 9X2 Header, 9-Pin, Dual rowINDUCTOR JTAG-10_Dup1 KEYB LED LED_Dup1 M25P16-VMN3PB 16 Mb (x1) Automotive Serial NOR Flash Memory, 75 MHz, 2.7 to 3.6 V, 8-pin SO8 Narrow (MN), TubeMHDR2X20 Header, 20-Pin, Dual rowMiniUSBB OSCPNP R RESISTOR RN RN_Dup1 R_Dup1 R_Dup2 R_Dup3 R_Dup5R_Dup6 SD SPEAKERSRV05-4SW KEY-DPDT ZTAbattery
标签： 黑金 cyclone4 ep4ce6f17c8 fpga
上传时间： 2021-12-22
上传用户：
Xilinx FPGA Virtex-7 全系列（AD集成封装库），IntLib后缀文件，PCB封装带3D视图，拆分后文件为PcbLib+SchLib格式，Altium Designer原理图库+PCB封装库，集成封装型号列表：Library Component Count : 157Name DESCRIPTION----------------------------------------------------------------------------------------------------XC7V2000T-1FHG1761C Virtex-7 FPGA, 1200 User I/Os, 36 GTX, 1760-Ball BGA, Speed Grade 1, Commerical Grade, Pb-FreeXC7V2000T-1FHG1761I Virtex-7 FPGA, 1200 User I/Os, 36 GTX, 1760-Ball BGA, Speed Grade 1, Industrial Grade, Pb-FreeXC7V2000T-1FLG1925C Virtex-7 FPGA, 1200 User I/Os, 16 GTX, 1924-Ball BGA, Speed Grade 1, Commercial Grade, Pb-FreeXC7V2000T-1FLG1925I Virtex-7 FPGA, 1200 User I/Os, 16 GTX, 1924-Ball BGA, Speed Grade 1, Industrial Grade, Pb-FreeXC7V2000T-2FHG1761C Virtex-7 FPGA, 1200 User I/Os, 36 GTX, 1760-Ball BGA, Speed Grade 2, Commerical Grade, Pb-FreeXC7V2000T-2FLG1925C Virtex-7 FPGA, 1200 User I/Os, 16 GTX, 1924-Ball BGA, Speed Grade 2, Commercial Grade, Pb-FreeXC7V2000T-2GFHG1761EVirtex-7 FPGA, 1200 User I/Os, 36 GTX, 1760-Ball BGA, Speed Grade 2G, Extended Grade, Pb-FreeXC7V2000T-2GFLG1925EVirtex-7 FPGA, 1200 User I/Os, 16 GTX, 1924-Ball BGA, Speed Grade 2G, Extended Grade, Pb-FreeXC7V2000T-2LFHG1761EVirtex-7 FPGA, 1200 User I/Os, 36 GTX, 1760-Ball BGA, Speed Grade 2L, Extended Grade, Pb-FreeXC7V2000T-2LFLG1925EVirtex-7 FPGA, 1200 User I/Os, 16 GTX, 1924-Ball BGA, Speed Grade 2L, Extended Grade, Pb-FreeXC7V585T-1FFG1157C Virtex-7 FPGA, 850 User I/Os, 20 GTX, 1156-Ball BGA, Speed Grade 1, Commercial Grade, Pb-FreeXC7V585T-1FFG1157I Virtex-7 FPGA, 850 User I/Os, 20 GTX, 1156-Ball BGA, Speed Grade 1, Industrial Grade, Pb-FreeXC7V585T-1FFG1761C Virtex-7 FPGA, 850 User I/Os, 36 GTX, 1760-Ball BGA, Speed Grade 1, Commercial Grade, Pb-FreeXC7V585T-1FFG1761I Virtex-7 FPGA, 850 User I/Os, 36 GTX, 1760-Ball BGA, Speed Grade 1, Industrial Grade, Pb-FreeXC7V585T-2FFG1157C Virtex-7 FPGA, 850 User I/Os, 20 GTX, 1156-Ball BGA, Speed Grade 2, Commercial Grade, Pb-FreeXC7V
上传时间： 2021-12-22
上传用户：aben
Xilinx FPGA Artix-7 全系列（AD集成封装库），IntLib后缀文件，PCB封装带3D视图，拆分后文件为PcbLib+SchLib格式，Altium Designer原理图库+PCB封装库，集成封装型号列表：Library Component Count : 48Name DESCRIPTION----------------------------------------------------------------------------------------------------XC7A100T-1CSG324C Artix-7 FPGA, 210 User I/Os, 0 GTP, 324-Ball BGA, Speed Grade 1, Commercial Grade, Pb-FreeXC7A100T-1CSG324I Artix-7 FPGA, 210 User I/Os, 0 GTP, 324-Ball BGA, Speed Grade 1, Industrial Grade, Pb-FreeXC7A100T-1FGG484C Artix-7 FPGA, 285 User I/Os, 4 GTP, 484-Ball BGA, Speed Grade 1, Commercial Grade, Pb-FreeXC7A100T-1FGG484I Artix-7 FPGA, 285 User I/Os, 4 GTP, 484-Ball BGA, Speed Grade 1, Industrial Grade, Pb-FreeXC7A100T-1FGG676C Artix-7 FPGA, 300 User I/Os, 8 GTP, 676-Ball BGA, Speed Grade 1, Commercial Grade, Pb-FreeXC7A100T-1FGG676I Artix-7 FPGA, 300 User I/Os, 8 GTP, 676-Ball BGA, Speed Grade 1, Industrial Grade, Pb-FreeXC7A100T-1FTG256C Artix-7 FPGA, 170 User I/Os, 0 GTP, 256-Ball BGA, Speed Grade 1, Commercial Grade, Pb-FreeXC7A100T-1FTG256I Artix-7 FPGA, 170 User I/Os, 0 GTP, 256-Ball BGA, Speed Grade 1, Industrial Grade, Pb-FreeXC7A100T-2CSG324C Artix-7 FPGA, 210 User I/Os, 0 GTP, 324-Ball BGA, Speed Grade 2, Commercial Grade, Pb-FreeXC7A100T-2CSG324I Artix-7 FPGA, 210 User I/Os, 0 GTP, 324-Ball BGA, Speed Grade 2, Industrial Grade, Pb-FreeXC7A100T-2FGG484C Artix-7 FPGA, 285 User I/Os, 4 GTP, 484-Ball BGA, Speed Grade 2, Commercial Grade, Pb-FreeXC7A100T-2FGG484I Artix-7 FPGA, 285 User I/Os, 4 GTP, 484-Ball BGA, Speed Grade 2, Industrial Grade, Pb-FreeXC7A100T-2FGG676C Artix-7 FPGA, 300 User I/Os, 8 GTP, 676-Ball BGA, Speed Grade 2, Commercial Grade, Pb-FreeXC7A100T-2FGG676I Artix-7 FPGA, 300 User I/Os, 8 GTP, 676-Ball BGA, Speed Grade 2, Industrial Grade, Pb-FreeXC7A100T-2FTG256C Artix-7 FPGA, 170 User I/Os, 0 GTP, 256-Ball BGA, Speed Grade 2, Commercial Grade, Pb-FreeXC7A100T-2FTG256I Artix-7 FPGA, 170 User I/Os, 0 GTP, 2
上传时间： 2021-12-22
上传用户：
基于DSP设计的数字化大功率电源数字化全桥变换器电源ALTIUM设计硬件原理图+PCB文件，包括主板和控制板2个硬件，均为4层板设计，ALTIUM设计的硬件工程文件，包括完整的原理图和PCB文件，可以做为你的设计参考。主板原理图器件如下：Library Component Count : 55Name DESCRIPTION----------------------------------------------------------------------------------------------------6CWQ09F Schottky Rectifier7416474HC16474LS1647805 7812 7815 7824 ACT45B 共模电感ARRESTER R27030059BAV99 R26010005BRIDGE R26060153CAPCB CD CON4 ConnectorComponent_1_1 D-1N5819 DiodeDEDIO-SMDELECTRO1 R21010742FUSE R27010205HOLHeader 3 Header, 3-PinHeader 6 Header, 6-PinHeader 7 Header, 7-PinIR1150S JQX-115F-I L0 L2 LBAV70 R26010012LM358MOSFET N NMOS-2 R26110100NPN R26080003OPTOISO1 R25030015PNP PNP TransistorR-NTCR20190006 R20190075R21020037 R21020037/工业B/消费C/瓷片电容/4700pF±20%/250Vac/Y2/Y5U/引脚间距7.5mmR26020054 R26020054/工业A/消费C/快恢复二极管/1000V/1A/1.7V/75ns/SMA/US1M-E3-61TR26030048 R26030048/工业A/消费B/肖特基二极管/1A/100V/0.79V/SMA/SS110LR26030097 R26030097/工业B/肖特基二极管/60V/1A/0.70V/SMA/B160R29030691 R29030691/防雷接地座/最大尺寸7.36*7*10/紫铜镀锡RES R20190099RES2 RES_1Res3 ResistorTL431 TRANS01TRANS7-9 Transformer UCC3804VARISTOR R27030060ZENERu型槽3.5x7
标签： tms320f28035 dsp 全桥变换器
上传时间： 2021-12-22
上传用户：aben
LTC2756 18位乘法串行输入电流输出数模转换器DAC模块ALTIUM原理图+PCB文件，硬件4层板设计，大小为66mmx39mm，ALTIUM设计的工程文件，包括完整的原理图和PCB文件，可以做为你的设计参考。 原理图器件列表： Library Component Count : 14 Name DESCRIPTION ---------------------------------------------------------------------------------------------------- AD8397ARDZ Imported Capacitor CAP.,1uF,X74,10V,10%,1206 Header 10X1 2.54 Header, 100mil, 2x1_1Header, 100mil, 2x1, Tin plated, TH Header, 100mil, 3x1 Header, 100mil, 3x1, Tin plated, TH KJDZ-2 快接端子 LT1012 LT1012 LT1360 LT1360 LTC2054_1 LTC2054 LTC2756AIG LTC2756AIG LTC6244 Imported LTC6655 LTC6655 Resistor RES.,1K OHMS,5%,1/16W,0603 SMA-KE CONNECTOR, SHEILDED, END LAUNCH JACK, GOLD PLATED, FOR 0.062 PCB, EDGE MOUNTED
标签： 数模转换器
上传时间： 2021-12-22
上传用户：
硬件描述语言（英文： Hardware DESCRIPTION Language ，简称： HDL ）是电子系统硬件行为描述、结构描述、数据流描述的语言。利用这种语言，数字电路系统的设计可以从顶层到底层（从抽象到具体）逐层描述自己的设计思想，用一系列分层次的模块来表示极其复杂的数字系统。然后，利用电子设计自动化（ EDA ）工具，逐层进行仿真验证，再把其中需要变为实际电路的模块组合，经过自动综合工具转换到门级电路网表。接下去，再用专用集成电路 ASIC 或现场可编程门阵列 FPGA 自动布局布线工具，把网表转换为要实现的具体电路布线结构
上传时间： 2021-12-24
上传用户：zhanglei193
MICRO-USB MICRO SD卡座 HDMI DDR3 按键ALTIUM 集成库（原理图库+3D PCB库）,.IntLib后缀文件，拆分后文件为PcbLib+SchLib格式，Altium Designer原理图库+PCB封装库，已验证使用，可以直接应用到你的项目开发。Library Component Count : 30Name DESCRIPTION----------------------------------------------------------------------------------------------------1_1.5KE100A_Dup1ANT IPEXAP2127K-ADJTRG1 STO23-5AP6212 QFN44P_120X120Banana_CPU CAP CapacitorCON3 Cap Pol1 Polarized Capacitor (Radial)DDR3-FBGA96DIODE DiodeDIP40-254 DIP40-254DOGESD_RClamp0524PA FPC-24HDMI miniHDMI-19P-SMDINDUCTOR_1JPO4 KEY-2PINLED NMOS_0 PMOS_0RES1R_P4 22R-1%SY8008B-AACSY8113BADC TF08F-1113A1-XXXB-SNRmicrosd-1113a1T_POINT_RUSBXTAL-2P XTAL-4P
上传时间： 2022-01-09
上传用户：bluedrops
1. Scope ......................................................................................................................................................................... 12. DDR4 SDRAM Package Pinout and Addressing ....................................................................................................... 22.1 DDR4 SDRAM Row for X4,X8 and X16 ................................................................................................................22.2 DDR4 SDRAM Ball Pitch........................................................................................................................................22.3 DDR4 SDRAM Columns for X4,X8 and X16 ..........................................................................................................22.4 DDR4 SDRAM X4/8 Ballout using MO-207......................................................................................................... 22.5 DDR4 SDRAM X16 Ballout using MO-207.............................................................................................................32.6 Pinout DESCRIPTION ..................................................................................................................................................52.7 DDR4 SDRAM Addressing.....................................................................................................................................73. Functional DESCRIPTION ...............................................................................................................................................83.1 Simplified State Diagram ....................................................................................................................................83.2 Basic Functionality..................................................................................................................................................93.3 RESET and Initialization Procedure .....................................................................................................................103.3.1 Power-up Initialization Sequence .............................................................................................................103.3.2 Reset Initialization with Stable Power ......................................................................................................113.4 Register Definition ................................................................................................................................................123.4.1 Programming the mode registers .............................................................................................................123.5 Mode Register ......................................................................................................................................................134. DDR4 SDRAM Command DESCRIPTION and Operation ............................................................................................. 244.1 Command Truth Table ..........................................................................................................................................244.2 CKE Truth Table ...................................................................................................................................................254.3 Burst Length, Type and Order ..............................................................................................................................264.3.1 BL8 Burst order with CRC Enabled .........................................................................................................264.4 DLL-off Mode & DLL on/off Switching procedure ................................................................................................274.4.1 DLL on/off switching procedure ...............................................................................................................274.4.2 DLL “on” to DLL “off” Procedure ..............................................................................................................274.4.3 DLL “off” to DLL “on” Procedure ..............................................................................................................284.5 DLL-off Mode........................................................................................................................................................294.6 Input Clock Frequency Change ............................................................................................................................304.7 Write Leveling.......................................................................................................................................................314.7.1 DRAM setting for write leveling & DRAM termination function in that mode ............................................324.7.2 Procedure DESCRIPTION .............................................................................................................................334.7.3 Write Leveling Mode Exit .........................................................................................................................34
标签： DDR4
上传时间： 2022-01-09
上传用户：
M.2的接口引脚定义，设计电路板的时候应该用的着
标签： pcie
上传时间： 2022-01-31
上传用户：jason_vip1
