数字集成电路设计Digital Integrated Circuit Design
This unique guide to designing digital VLSI circuits takes a top-down approach, reflectin...
Clocking技术资料
📦 资源总数：11
💻 源代码：196
🔌 电路图：3
📚 Clocking全部资料 (11个)
逐次逼近式AD转换器研究
A tutorial on SAR type A/D converters, this note contains detailed information on several 12-bit c...
Clocking Options for Stellaris
The main oscillator allows either a crystal or single-ended input clock signal. Cost-sensitiveapplic...
用单片机配置FPGA—PLD设计技巧
用单片机配置FPGA—PLD设计技巧 Configuration/Program Method for Altera Device Configure the FLEX Device You can ...
XAPP1065 - 利用Spartan-6 FPGA设计扩频时钟发生器
Consumer display applications commonly use high-speed LVDS interfaces to transfer videoda...
带有SerDes接口的PLB千兆位级以太网MAC
This application note describes a reference system which illustrates how to build an embeddedPower...
XAPP1065 - 利用Spartan-6 FPGA设计扩频时钟发生器
Consumer display applications commonly use high-speed LVDS interfaces to transfer videoda...
tas3204
The TAS3204 is a highly-integrated audio system-on-chip (SOC) consisting of a fully-program...
Vivado时序约束
Synopsys' widely-used design constraints format, known as SDC, describes the "design intent" and sur...
vivado集成开发环境时序约束介绍
本文主要介绍如何在Wado设计套件中进行时序约束，原文出自 xilinx中文社区。1 Timing Constraints in Vivado-UCF to xdcVivado软件相比于sE的一大转变...