This is GPS in matlab calculatePseudoranges finds relative pseudoranges for all satellites listed in CHANNELLIST at the specified millisecond of the processed signal. The pseudoranges contain unknown receiver clock offset. It can be found by the least squares position search procedure.
标签： calculatePseudoranges pseudoranges satellites relative
上传时间： 2017-03-09
上传用户：时代电子小智
Enhanced version of the Serial Peripheral Interface available on Motorola s MC68HC11 family of CPUs.Enhancements include a wider supported operating frequency range, 4deep read and write fifos, and programmable transfer count dependent interrupt generation. As with the SPI found in MC68HC11 processors the core features programmable clock phase [CPHA] and clock polarity [CPOL]. The core features an 8bit wishbone interface. Very simple, very small.
标签： Peripheral Interface available Enhanced
上传时间： 2014-12-06
上传用户：invtnewer
Decimal counter which is counting from 256 to 0. After that there will appear logic "1" in out. You can stop counting by pressing sequence. I called it detonation clock :]
标签： counting Decimal counter appear
上传时间： 2014-10-13
上传用户：731140412
TLC548和TLC549是以8位开关电容逐次逼近A/D转换器为基础而构造的CMOS A/D转换器。它们设 计成能通过3态数据输出和模拟输入与微处理器或外围设备串行接口。TLC548和TLC549仅用输入/输出时 钟（I/O CLOCK） 和芯片选择（CS） 输入作数据控制。TLC548的最高I/O CLOCK输入频率为2.048MHz， 而TLC549的I/O CLOCK输入频率最高可达1.1MHz。 有关与大多数通用微处理器接口的详细资料已由工厂 准备好，可供使用。
上传时间： 2013-11-28
上传用户：aig85
This example sets up the PLL in x10/2 mode, divides SYSCLKOUT by six to reach a 25Mhz HSPCLK (assuming a 30Mhz XCLKIN). The clock divider in the ADC is not used so that the ADC will see the 25Mhz on the HSPCLK. Interrupts are enabled and the EVA is setup to generate a periodic ADC SOC on SEQ1. Two channels are converted, ADCINA3 and ADCINA2.
标签： SYSCLKOUT example divides HSPCLK
上传时间： 2014-01-25
上传用户：ljt101007
这是MFC Windows程序设计（第2版），书上的代码。第14章，计时器，CLOCK应用程序，空闲处理的编程，供大家参考。
上传时间： 2013-12-24
上传用户：wangyi39
三星程式范例，八位元的 timer, counter, serial I/O, clock switching, power down, key scan, A to D, software generated LCD control, ...
上传时间： 2013-12-17
上传用户：zhengzg
Pure hardware JPEG Encoder design. Package includes vhdl source code, test bench, detail design document. Written in VHDL. Verified on Xilinx XC4VLX25. Rncode 320x240 bmp picture in 3ms at 50 quality, 100Mhz clock.
标签： design hardware includes Encoder
上传时间： 2013-12-15
上传用户：王者A
本模拟I2C软件包包含了I2C操作的底层子程序，使用前要定义好SCL和SDA。在标准8051模式(12 Clock)下,对主频要求是不高于12MHz
上传时间： 2013-12-27
上传用户：330402686
This manual describes SAMSUNG s S3C2410A 16/32-bit RISC microprocessor. This product is designed to provide hand-held devices and general applications with cost-effective, low-power, and high-performance micro-controller solution in small die size. To reduce total system cost, the S3C2410A includes the following components separate 16KB Instruction and 16KB Data Cache, MMU to handle virtual memory management, LCD Controller (STN & TFT), NAND Flash Boot Loader, System Manager (chip select logic and SDRAM Controller), 3-ch UART, 4-ch DMA, 4-ch Timers with PWM, I/O Ports, RTC, 8-ch 10-bit ADC and Touch Screen Interface, IIC-BUS Interface, IIS-BUS Interface, USB Host, USB Device, SD Host & Multi-Media Card Interface, 2-ch SPI and PLL for clock generation.
标签： This microprocessor describes S3C2410A
上传时间： 2013-11-30
上传用户：GavinNeko
