There has long been a need for portable ultrasoundsystems that have good resolution at affordable costpoints. Portable systems enable healthcare providersto use ultrasound in remote locations such asdisaster zones, developing regions, and battlefields,where it was not previously practical to do so.
上传时间： 2015-01-01
上传用户：hfnishi
PADS-PowerLogic and PowerPcb实用教程
标签： PADS-PowerLogic PowerPcb and 实用教程
上传时间： 2014-01-24
上传用户：qiaoyue
This white paper discusses how market trends, the need for increased productivity, and new legislation have accelerated the use of safety systems in industrial machinery. This TÜV-qualified FPGA design methodology is changing the paradigms of safety designs and will greatly reduce development effort, system complexity, and time to market. This allows FPGA users to design their own customized safety controllers and provides a significant competitive advantage over traditional microcontroller or ASIC-based designs. Introduction The basic motivation of deploying functional safety systems is to ensure safe operation as well as safe behavior in cases of failure. Examples of functional safety systems include train brakes, proximity sensors for hazardous areas around machines such as fast-moving robots, and distributed control systems in process automation equipment such as those used in petrochemical plants. The International Electrotechnical Commission’s standard, IEC 61508: “Functional safety of electrical/electronic/programmable electronic safety-related systems,” is understood as the standard for designing safety systems for electrical, electronic, and programmable electronic (E/E/PE) equipment. This standard was developed in the mid-1980s and has been revised several times to cover the technical advances in various industries. In addition, derivative standards have been developed for specific markets and applications that prescribe the particular requirements on functional safety systems in these industry applications. Example applications include process automation (IEC 61511), machine automation (IEC 62061), transportation (railway EN 50128), medical (IEC 62304), automotive (ISO 26262), power generation, distribution, and transportation. 图Figure 1. Local Safety System
上传时间： 2013-11-14
上传用户：zoudejile
Nios II软件构建工具入门 The Nios® II Software Build Tools (SBT) allows you to construct a wide variety of complex embedded software systems using a command-line interface. From this interface, you can execute Software Built Tools command utilities, and use scripts other tools) to combine the command utilities in many useful ways. This chapter introduces you to project creation with the SBT at the command line This chapter includes the following sections: ■ “Advantages of Command-Line Software Development” ■ “Outline of the Nios II SBT Command-Line Interface” ■ “Getting Started in the SBT Command Line” ■ “Software Build Tools Scripting Basics” on page 3–8
上传时间： 2013-11-15
上传用户：nanxia
通过以太网远程配置Nios II 处理器 应用笔记 Firmware in embedded hardware systems is frequently updated over the Ethernet. For embedded systems that comprise a discrete microprocessor and the devices it controls, the firmware is the software image run by the microprocessor. When the embedded system includes an FPGA, firmware updates include updates of the hardware image on the FPGA. If the FPGA includes a Nios® II soft processor, you can upgrade both the Nios II processor—as part of the FPGA image—and the software that the Nios II processor runs, in a single remote configuration session.
上传时间： 2013-11-22
上传用户：chaisz
面向Eclips的Nios II软件构建工具手册 The Nios® II Software Build Tools (SBT) for Eclipse™ is a set of plugins based on the Eclipse™ framework and the Eclipse C/C++ development toolkit (CDT) plugins. The Nios II SBT for Eclipse provides a consistent development platform that works for all Nios II embedded processor systems. You can accomplish all Nios II software development tasks within Eclipse, including creating, editing, building, running, debugging, and profiling programs.
上传时间： 2013-11-02
上传用户：瓦力瓦力hong
怎样使用Nios II处理器来构建多处理器系统 Chapter 1. Creating Multiprocessor Nios II Systems Introduction to Nios II Multiprocessor Systems . . . . . . . . . . . . . . 1–1 Benefits of Hierarchical Multiprocessor Systems . . . . . . . . . . . . . . . 1–2 Nios II Multiprocessor Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2 Multiprocessor Tutorial Prerequisites . . . . . . . . . . . . . . . . . . . . . . . 1–3 Hardware Designs for Peripheral Sharing . . . . . . . . . . . .. . . . . . . . 1–3 Autonomous Multiprocessors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–3 Multiprocessors that Share Peripherals . . . . . . . . . . . . . . . . . . . . . . 1–4 Sharing Peripherals in a Multiprocessor System . . . . . . . . . . . . . . . . . 1–4 Sharing Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–6 The Hardware Mutex Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–7 Sharing Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . 1–8 Overlapping Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–8 Software Design Considerations for Multiple Processors . . .. . . . . 1–9 Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–9 Boot Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1–13 Debugging Nios II Multiprocessor Designs . . . . . . . . . . . . . . . . 1–15 Design Example: The Dining Philosophers’ Problem . . . . .. . . 1–15 Hardware and Software Requirements . . . . . . . . . . . . . . . .. . . 1–16 Installation Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–17 Creating the Hardware System . . . . . . . . . . . . . . .. . . . . . 1–17 Getting Started with the multiprocessor_tutorial_start Design Example 1–17 Viewing a Philosopher System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–18 Philosopher System Pipeline Bridges . . . . . . . . . . . . . . . . . . . . . 1–19 Adding Philosopher Subsystems . . . . . . . . . . . . . . . . . . . . . . . . . . 1–21 Connecting the Philosopher Subsystems . . . . . . . . . . . . .. . . . . 1–22 Viewing the Complete System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–27 Generating and Compiling the System . . . . . . . . . . . . . . . . . .. 1–28
上传时间： 2013-11-21
上传用户：lo25643
Nios II 系列处理器配置选项:This chapter describes the Nios® II Processor parameter editor in Qsys and SOPC Builder. The Nios II Processor parameter editor allows you to specify the processor features for a particular Nios II hardware system. This chapter covers the features of the Nios II processor that you can configure with the Nios II Processor parameter editor; it is not a user guide for creating complete Nios II processor systems.
上传时间： 2015-01-01
上传用户：mahone
Trademarks and service marks of Cadence Design Systems, Inc. (Cadence) contained in this document are attributed to Cadence with the appropriate symbol.
上传时间： 2013-10-14
上传用户：chukeey
Today’s digital systems combine a myriad of chips with different voltage configurations.Designers must interface 2.5V processors with 3.3V memories—both RAM and ROM—as wellas 5V buses and multiple peripheral chips. Each chip has specific power supply needs. CPLDsare ideal for handling the multi-voltage interfacing, but do require forethought to ensure correctoperation.
上传时间： 2013-11-10
上传用户：yy_cn
