代码搜索：vhdl
找到约 10,000 项符合「vhdl」的源代码
代码结果 10,000
www.eeworm.com/read/287512/8684558
asm _vhdl.asm
www.eeworm.com/read/287512/8684578
asm _vhdl.asm
www.eeworm.com/read/287512/8684592
asm _vhdl.asm
www.eeworm.com/read/431369/8686187
vhdl scope.vhdl
-- Name: Scope Controller
-- Version: 1.4 Partially Tested
-- Date: 06Sep2005 Adi
-- Function: XC9572 controller for eOscope
--
-- Descrition:
-- Keyboard interface, ADC control
www.eeworm.com/read/386951/8716543
pdf vhdl.pdf
www.eeworm.com/read/385850/8785882
pdf vhdl.pdf
www.eeworm.com/read/286149/8787385
txt vhdl.txt
/*端口信号说明：
clk 输入时钟信号
reset 复位信号，低电平有效
din 按键输入信号
d 波形的离散值输出*/
module wave(clk,reset,din,d);
input clk,reset,din;
output [7:0] d;
reg [7:0] d;
//中间变量寄存器
reg [7:0]
www.eeworm.com/read/286093/8788549
vhdl fpq.vhdl
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity fpq is
port(clkin:in std_logic;
clkout:out std_logic);
end fpq;
architecture
www.eeworm.com/read/286093/8788646
vhdl dsq.vhdl
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity dsq is
port
(en1,hold,clkin1:in std_logic;
q2:out std_logic;
dat
www.eeworm.com/read/286093/8788649
vhdl ymq.vhdl
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ymq is
port
(int:in std_logic_vector(3 downto 0);
out7:out std_logic_