dsq.vhdl

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity dsq is
  port
    (en1,hold,clkin1:in std_logic;
     q2:out std_logic;
	   data1:out std_logic_vector(3 downto 0);
	   data2:out std_logic_vector(3 downto 0));     
end dsq;
architecture Behavioral of dsq is
    
    signal num:integer range 0 to 10 ; 
    signal t1: std_logic_vector(3 downto 0);
    signal t2: std_logic_vector(3 downto 0);
    signal q0: std_logic;
 begin
    
    process(en1,clkin1,num) 
    variable num1:integer range 0 to 1000;
    
      begin
	      if en1='0' then 
	         q0<='0'; num<=10; num1:=0;
	      elsif rising_edge (clkin1) then
	         if hold='1' then
		       	 q0<='1';num1:=0;
			      num<=num;
		       else 
		          if num=0 then
		            q0<='1';
			       else 
			         if num1=1000 then 
				    num1:=0;
				    num<=num-1;q0<='0';
				    else 
				      num<=num;q0<='0';num1:=num1+1;
			       end if;
	         end if;
	     end if;
	
	end if;	
    end process;
    
     q2<=q0;
process(en1,num)
     begin
	    	if en1='1' then
        case num is
             
		   when 10 =>t1<="0001";  t2<="0000";
		   when  9 =>t1<="0000";  t2<="1001";
		   when  8 =>t1<="0000";  t2<="1000";
		   when  7 =>t1<="0000";  t2<="0111";    	 
		   when  6 =>t1<="0000";  t2<="0110";
		   when  5 =>t1<="0000";  t2<="0101";
		   when  4 =>t1<="0000";  t2<="0100";
		   when  3 =>t1<="0000";  t2<="0011";
		   when  2 =>t1<="0000";  t2<="0010";
		   when  1 =>t1<="0000";  t2<="0001";
		   when  0 =>t1<="0000";  t2<="0000";
		   when others =>t1<="1111";  t2<="1111";
	     end case;
	  else 
	     t1<="1111";t2<="1111"; 
	  end if;
  end process;
data1<=t1; data2<=t2;
end Behavioral;